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Merge branch 'pci/misc' into next
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* pci/misc:
  PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available
  PCI: exynos: Add I/O access wrappers
  PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc()
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Bjorn Helgaas committed Aug 29, 2013
2 parents 2e8b5f6 + 3dc48af commit e89c331
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Showing 3 changed files with 184 additions and 173 deletions.
62 changes: 38 additions & 24 deletions drivers/acpi/pci_root.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -378,6 +378,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
struct acpi_pci_root *root;
u32 flags, base_flags;
acpi_handle handle = device->handle;
bool no_aspm = false, clear_aspm = false;

root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
if (!root)
Expand Down Expand Up @@ -437,27 +438,6 @@ static int acpi_pci_root_add(struct acpi_device *device,
flags = base_flags = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
acpi_pci_osc_support(root, flags);

/*
* TBD: Need PCI interface for enumeration/configuration of roots.
*/

/*
* Scan the Root Bridge
* --------------------
* Must do this prior to any attempt to bind the root device, as the
* PCI namespace does not get created until this call is made (and
* thus the root bridge's pci_dev does not exist).
*/
root->bus = pci_acpi_scan_root(root);
if (!root->bus) {
dev_err(&device->dev,
"Bus %04x:%02x not present in PCI namespace\n",
root->segment, (unsigned int)root->secondary.start);
result = -ENODEV;
goto end;
}

/* Indicate support for various _OSC capabilities. */
if (pci_ext_cfg_avail())
flags |= OSC_EXT_PCI_CONFIG_SUPPORT;
if (pcie_aspm_support_enabled()) {
Expand All @@ -471,7 +451,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
if (ACPI_FAILURE(status)) {
dev_info(&device->dev, "ACPI _OSC support "
"notification failed, disabling PCIe ASPM\n");
pcie_no_aspm();
no_aspm = true;
flags = base_flags;
}
}
Expand Down Expand Up @@ -503,7 +483,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
* We have ASPM control, but the FADT indicates
* that it's unsupported. Clear it.
*/
pcie_clear_aspm(root->bus);
clear_aspm = true;
}
} else {
dev_info(&device->dev,
Expand All @@ -512,14 +492,48 @@ static int acpi_pci_root_add(struct acpi_device *device,
acpi_format_exception(status), flags);
dev_info(&device->dev,
"ACPI _OSC control for PCIe not granted, disabling ASPM\n");
pcie_no_aspm();
/*
* We want to disable ASPM here, but aspm_disabled
* needs to remain in its state from boot so that we
* properly handle PCIe 1.1 devices. So we set this
* flag here, to defer the action until after the ACPI
* root scan.
*/
no_aspm = true;
}
} else {
dev_info(&device->dev,
"Unable to request _OSC control "
"(_OSC support mask: 0x%02x)\n", flags);
}

/*
* TBD: Need PCI interface for enumeration/configuration of roots.
*/

/*
* Scan the Root Bridge
* --------------------
* Must do this prior to any attempt to bind the root device, as the
* PCI namespace does not get created until this call is made (and
* thus the root bridge's pci_dev does not exist).
*/
root->bus = pci_acpi_scan_root(root);
if (!root->bus) {
dev_err(&device->dev,
"Bus %04x:%02x not present in PCI namespace\n",
root->segment, (unsigned int)root->secondary.start);
result = -ENODEV;
goto end;
}

if (clear_aspm) {
dev_info(&device->dev, "Disabling ASPM (FADT indicates it is unsupported)\n");
pcie_clear_aspm(root->bus);
}
if (no_aspm)
pcie_no_aspm();

pci_acpi_add_bus_pm_notifier(device, root->bus);
if (device->wakeup.flags.run_wake)
device_set_run_wake(root->bus->bridge, true);
Expand Down
160 changes: 91 additions & 69 deletions drivers/pci/host/pci-exynos.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -91,19 +91,49 @@ struct exynos_pcie {
#define PCIE_PHY_TRSV3_RXCDR 0x2ec
#define PCIE_PHY_TRSV3_LVCC 0x31c

static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
{
writel(val, pcie->elbi_base + reg);
}

static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg)
{
return readl(pcie->elbi_base + reg);
}

static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
{
writel(val, pcie->phy_base + reg);
}

static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg)
{
return readl(pcie->phy_base + reg);
}

static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
{
writel(val, pcie->block_base + reg);
}

static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg)
{
return readl(pcie->block_base + reg);
}

static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
{
u32 val;
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

if (on) {
val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
} else {
val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
}
}

Expand All @@ -113,109 +143,103 @@ static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);

if (on) {
val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
} else {
val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
}
}

static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
{
u32 val;
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
void __iomem *elbi_base = exynos_pcie->elbi_base;

val = readl(elbi_base + PCIE_CORE_RESET);
val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
val &= ~PCIE_CORE_RESET_ENABLE;
writel(val, elbi_base + PCIE_CORE_RESET);
writel(0, elbi_base + PCIE_PWR_RESET);
writel(0, elbi_base + PCIE_STICKY_RESET);
writel(0, elbi_base + PCIE_NONSTICKY_RESET);
exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET);
exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET);
exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);
}

static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
{
u32 val;
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
void __iomem *elbi_base = exynos_pcie->elbi_base;
void __iomem *block_base = exynos_pcie->block_base;

val = readl(elbi_base + PCIE_CORE_RESET);
val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
val |= PCIE_CORE_RESET_ENABLE;
writel(val, elbi_base + PCIE_CORE_RESET);
writel(1, elbi_base + PCIE_STICKY_RESET);
writel(1, elbi_base + PCIE_NONSTICKY_RESET);
writel(1, elbi_base + PCIE_APP_INIT_RESET);
writel(0, elbi_base + PCIE_APP_INIT_RESET);
writel(1, block_base + PCIE_PHY_MAC_RESET);

exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET);
exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET);
exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET);
exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET);
exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);
}

static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)
{
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
void __iomem *block_base = exynos_pcie->block_base;

writel(0, block_base + PCIE_PHY_MAC_RESET);
writel(1, block_base + PCIE_PHY_GLOBAL_RESET);
exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);
exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);
}

static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
{
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
void __iomem *elbi_base = exynos_pcie->elbi_base;
void __iomem *block_base = exynos_pcie->block_base;

writel(0, block_base + PCIE_PHY_GLOBAL_RESET);
writel(1, elbi_base + PCIE_PWR_RESET);
writel(0, block_base + PCIE_PHY_COMMON_RESET);
writel(0, block_base + PCIE_PHY_CMN_REG);
writel(0, block_base + PCIE_PHY_TRSVREG_RESET);
writel(0, block_base + PCIE_PHY_TRSV_RESET);

exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);
exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);
exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG);
exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET);
exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);
}

static void exynos_pcie_init_phy(struct pcie_port *pp)
{
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
void __iomem *phy_base = exynos_pcie->phy_base;

/* DCC feedback control off */
writel(0x29, phy_base + PCIE_PHY_DCC_FEEDBACK);
exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);

/* set TX/RX impedance */
writel(0xd5, phy_base + PCIE_PHY_IMPEDANCE);
exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE);

/* set 50Mhz PHY clock */
writel(0x14, phy_base + PCIE_PHY_PLL_DIV_0);
writel(0x12, phy_base + PCIE_PHY_PLL_DIV_1);
exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0);
exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1);

/* set TX Differential output for lane 0 */
writel(0x7f, phy_base + PCIE_PHY_TRSV0_DRV_LVL);
exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);

/* set TX Pre-emphasis Level Control for lane 0 to minimum */
writel(0x0, phy_base + PCIE_PHY_TRSV0_EMP_LVL);
exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL);

/* set RX clock and data recovery bandwidth */
writel(0xe7, phy_base + PCIE_PHY_PLL_BIAS);
writel(0x82, phy_base + PCIE_PHY_TRSV0_RXCDR);
writel(0x82, phy_base + PCIE_PHY_TRSV1_RXCDR);
writel(0x82, phy_base + PCIE_PHY_TRSV2_RXCDR);
writel(0x82, phy_base + PCIE_PHY_TRSV3_RXCDR);
exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS);
exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR);
exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR);
exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR);
exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR);

/* change TX Pre-emphasis Level Control for lanes */
writel(0x39, phy_base + PCIE_PHY_TRSV0_EMP_LVL);
writel(0x39, phy_base + PCIE_PHY_TRSV1_EMP_LVL);
writel(0x39, phy_base + PCIE_PHY_TRSV2_EMP_LVL);
writel(0x39, phy_base + PCIE_PHY_TRSV3_EMP_LVL);
exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL);

/* set LVCC */
writel(0x20, phy_base + PCIE_PHY_TRSV0_LVCC);
writel(0xa0, phy_base + PCIE_PHY_TRSV1_LVCC);
writel(0xa0, phy_base + PCIE_PHY_TRSV2_LVCC);
writel(0xa0, phy_base + PCIE_PHY_TRSV3_LVCC);
exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC);
exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC);
exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC);
exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);
}

static void exynos_pcie_assert_reset(struct pcie_port *pp)
Expand All @@ -233,9 +257,6 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
u32 val;
int count = 0;
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
void __iomem *elbi_base = exynos_pcie->elbi_base;
void __iomem *block_base = exynos_pcie->block_base;
void __iomem *phy_base = exynos_pcie->phy_base;

if (dw_pcie_link_up(pp)) {
dev_err(pp->dev, "Link already up\n");
Expand All @@ -253,9 +274,9 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
exynos_pcie_init_phy(pp);

/* pulse for common reset */
writel(1, block_base + PCIE_PHY_COMMON_RESET);
exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);
udelay(500);
writel(0, block_base + PCIE_PHY_COMMON_RESET);
exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);

/* de-assert core reset */
exynos_pcie_deassert_core_reset(pp);
Expand All @@ -267,15 +288,18 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
exynos_pcie_assert_reset(pp);

/* assert LTSSM enable */
writel(PCIE_ELBI_LTSSM_ENABLE, elbi_base + PCIE_APP_LTSSM_ENABLE);
exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
PCIE_APP_LTSSM_ENABLE);

/* check if the link is up or not */
while (!dw_pcie_link_up(pp)) {
mdelay(100);
count++;
if (count == 10) {
while (readl(phy_base + PCIE_PHY_PLL_LOCKED) == 0) {
val = readl(block_base + PCIE_PHY_PLL_LOCKED);
while (exynos_phy_readl(exynos_pcie,
PCIE_PHY_PLL_LOCKED) == 0) {
val = exynos_blk_readl(exynos_pcie,
PCIE_PHY_PLL_LOCKED);
dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
}
dev_err(pp->dev, "PCIe Link Fail\n");
Expand All @@ -292,23 +316,21 @@ static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
{
u32 val;
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
void __iomem *elbi_base = exynos_pcie->elbi_base;

val = readl(elbi_base + PCIE_IRQ_PULSE);
writel(val, elbi_base + PCIE_IRQ_PULSE);
val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
return;
}

static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
{
u32 val;
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
void __iomem *elbi_base = exynos_pcie->elbi_base;

/* enable INTX interrupt */
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
writel(val, elbi_base + PCIE_IRQ_EN_PULSE);
exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
return;
}

Expand Down Expand Up @@ -369,7 +391,7 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
static int exynos_pcie_link_up(struct pcie_port *pp)
{
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
u32 val = readl(exynos_pcie->elbi_base + PCIE_ELBI_RDLH_LINKUP);
u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);

if (val == PCIE_ELBI_LTSSM_ENABLE)
return 1;
Expand Down
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