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drm/msm/a6xx: Mostly implement A7xx gpu_state
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Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/559289/
Signed-off-by: Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored and Rob Clark committed Oct 9, 2023
1 parent 88a0997 commit e997ae5
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Showing 2 changed files with 110 additions and 3 deletions.
52 changes: 51 additions & 1 deletion drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -948,6 +948,18 @@ static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu)
return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14;
}

static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu)
{
/*
* The value at CP_ROQ_THRESHOLDS_2[20:31] is in 4dword units.
* That register however is not directly accessible from APSS on A7xx.
* Program the SQE_UCODE_DBG_ADDR with offset=0x70d3 and read the value.
*/
gpu_write(gpu, REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 0x70d3);

return 4 * (gpu_read(gpu, REG_A6XX_CP_SQE_UCODE_DBG_DATA) >> 20);
}

/* Read a block of data from an indexed register pair */
static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
Expand Down Expand Up @@ -1019,8 +1031,40 @@ static void a6xx_get_indexed_registers(struct msm_gpu *gpu,

/* Restore the size in the hardware */
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size);
}

static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
int i, indexed_count, mempool_count;

indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed);

a6xx_state->nr_indexed_regs = count;
a6xx_state->indexed_regs = state_kcalloc(a6xx_state,
indexed_count + mempool_count,
sizeof(*a6xx_state->indexed_regs));
if (!a6xx_state->indexed_regs)
return;

a6xx_state->nr_indexed_regs = indexed_count + mempool_count;

/* First read the common regs */
for (i = 0; i < indexed_count; i++)
a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_indexed_reglist[i],
&a6xx_state->indexed_regs[i]);

gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2));
gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, 0, BIT(2));

/* Get the contents of the CP_BV mempool */
for (i = 0; i < mempool_count; i++)
a6xx_get_indexed_regs(gpu, a6xx_state, a7xx_cp_bv_mempool_indexed,
&a6xx_state->indexed_regs[indexed_count - 1 + i]);

gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0);
gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0);
return;
}

struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
Expand Down Expand Up @@ -1056,6 +1100,12 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
return &a6xx_state->base;

/* Get the banks of indexed registers */
if (adreno_is_a7xx(adreno_gpu)) {
a7xx_get_indexed_registers(gpu, a6xx_state);
/* Further codeflow is untested on A7xx. */
return &a6xx_state->base;
}

a6xx_get_indexed_registers(gpu, a6xx_state);

/*
Expand Down
61 changes: 59 additions & 2 deletions drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -338,6 +338,28 @@ static const struct a6xx_registers a6xx_vbif_reglist =
static const struct a6xx_registers a6xx_gbif_reglist =
REGS(a6xx_gbif_registers, 0, 0);

static const u32 a7xx_ahb_registers[] = {
/* RBBM_STATUS */
0x210, 0x210,
/* RBBM_STATUS2-3 */
0x212, 0x213,
};

static const u32 a7xx_gbif_registers[] = {
0x3c00, 0x3c0b,
0x3c40, 0x3c42,
0x3c45, 0x3c47,
0x3c49, 0x3c4a,
0x3cc0, 0x3cd1,
};

static const struct a6xx_registers a7xx_ahb_reglist[] = {
REGS(a7xx_ahb_registers, 0, 0),
};

static const struct a6xx_registers a7xx_gbif_reglist =
REGS(a7xx_gbif_registers, 0, 0);

static const u32 a6xx_gmu_gx_registers[] = {
/* GMU GX */
0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
Expand Down Expand Up @@ -384,14 +406,17 @@ static const struct a6xx_registers a6xx_gmu_reglist[] = {
};

static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);

static struct a6xx_indexed_registers {
struct a6xx_indexed_registers {
const char *name;
u32 addr;
u32 data;
u32 count;
u32 (*count_fn)(struct msm_gpu *gpu);
} a6xx_indexed_reglist[] = {
};

static struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
Expand All @@ -402,11 +427,43 @@ static struct a6xx_indexed_registers {
REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
};

static struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
{ "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL },
{ "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL },
{ "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL },
{ "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,
REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL },
{ "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL },
{ "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL },
{ "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL },
{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },
};

static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
};

static struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
{ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },
{ "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL },
};

#define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }

static const struct a6xx_debugbus_block {
Expand Down

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