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iavf: define Rx descriptors as qwords
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The union iavf_32byte_rx_desc consists of two unnamed structs defined
inside. One of them represents legacy 32 byte descriptor and second the
16 byte descriptor (extended to 32 byte). Each of them consists of
bunch of unions, structs and __le fields that represent specific fields
in descriptor.

This commit changes the representation of iavf_32byte_rx_desc union
to store four __le64 fields (qw0, qw1, qw2, qw3) that represent
quad-words. Those quad-words will be then accessed by calling
leXY_get_bits macros in upcoming commits.

Suggested-by: Alexander Lobakin <aleksander.lobakin@intel.com>
Tested-by: Rafal Romanowski <rafal.romanowski@intel.com>
Signed-off-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
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Mateusz Polchlopek authored and Tony Nguyen committed Feb 14, 2025
1 parent ce5cf4a commit e9f476d
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Showing 5 changed files with 77 additions and 111 deletions.
2 changes: 1 addition & 1 deletion drivers/net/ethernet/intel/iavf/iavf.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,7 @@ struct iavf_vsi {

#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)

#define IAVF_RX_DESC(R, i) (&(((union iavf_32byte_rx_desc *)((R)->desc))[i]))
#define IAVF_RX_DESC(R, i) (&(((struct iavf_rx_desc *)((R)->desc))[i]))
#define IAVF_TX_DESC(R, i) (&(((struct iavf_tx_desc *)((R)->desc))[i]))
#define IAVF_TX_CTXTDESC(R, i) \
(&(((struct iavf_tx_context_desc *)((R)->desc))[i]))
Expand Down
6 changes: 3 additions & 3 deletions drivers/net/ethernet/intel/iavf/iavf_trace.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,7 @@ DECLARE_EVENT_CLASS(
iavf_rx_template,

TP_PROTO(struct iavf_ring *ring,
union iavf_32byte_rx_desc *desc,
struct iavf_rx_desc *desc,
struct sk_buff *skb),

TP_ARGS(ring, desc, skb),
Expand Down Expand Up @@ -140,15 +140,15 @@ DECLARE_EVENT_CLASS(
DEFINE_EVENT(
iavf_rx_template, iavf_clean_rx_irq,
TP_PROTO(struct iavf_ring *ring,
union iavf_32byte_rx_desc *desc,
struct iavf_rx_desc *desc,
struct sk_buff *skb),

TP_ARGS(ring, desc, skb));

DEFINE_EVENT(
iavf_rx_template, iavf_clean_rx_irq_rx,
TP_PROTO(struct iavf_ring *ring,
union iavf_32byte_rx_desc *desc,
struct iavf_rx_desc *desc,
struct sk_buff *skb),

TP_ARGS(ring, desc, skb));
Expand Down
56 changes: 30 additions & 26 deletions drivers/net/ethernet/intel/iavf/iavf_txrx.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -766,7 +766,7 @@ int iavf_setup_rx_descriptors(struct iavf_ring *rx_ring)
u64_stats_init(&rx_ring->syncp);

/* Round up to nearest 4K */
rx_ring->size = rx_ring->count * sizeof(union iavf_32byte_rx_desc);
rx_ring->size = rx_ring->count * sizeof(struct iavf_rx_desc);
rx_ring->size = ALIGN(rx_ring->size, 4096);
rx_ring->desc = dma_alloc_coherent(fq.pp->p.dev, rx_ring->size,
&rx_ring->dma, GFP_KERNEL);
Expand Down Expand Up @@ -845,7 +845,7 @@ bool iavf_alloc_rx_buffers(struct iavf_ring *rx_ring, u16 cleaned_count)
.count = rx_ring->count,
};
u16 ntu = rx_ring->next_to_use;
union iavf_rx_desc *rx_desc;
struct iavf_rx_desc *rx_desc;

/* do nothing if no valid netdev defined */
if (!rx_ring->netdev || !cleaned_count)
Expand All @@ -863,7 +863,7 @@ bool iavf_alloc_rx_buffers(struct iavf_ring *rx_ring, u16 cleaned_count)
/* Refresh the desc even if buffer_addrs didn't change
* because each write-back erases this info.
*/
rx_desc->read.pkt_addr = cpu_to_le64(addr);
rx_desc->qw0 = cpu_to_le64(addr);

rx_desc++;
ntu++;
Expand All @@ -873,7 +873,7 @@ bool iavf_alloc_rx_buffers(struct iavf_ring *rx_ring, u16 cleaned_count)
}

/* clear the status bits for the next_to_use descriptor */
rx_desc->wb.qword1.status_error_len = 0;
rx_desc->qw1 = 0;

cleaned_count--;
} while (cleaned_count);
Expand Down Expand Up @@ -901,19 +901,18 @@ bool iavf_alloc_rx_buffers(struct iavf_ring *rx_ring, u16 cleaned_count)
* @skb: skb currently being received and modified
* @rx_desc: the receive descriptor
**/
static void iavf_rx_checksum(struct iavf_vsi *vsi,
struct sk_buff *skb,
union iavf_rx_desc *rx_desc)
static void iavf_rx_checksum(struct iavf_vsi *vsi, struct sk_buff *skb,
struct iavf_rx_desc *rx_desc)
{
struct libeth_rx_pt decoded;
u32 rx_error, rx_status;
bool ipv4, ipv6;
u8 ptype;
u64 qword;
u32 ptype;

skb->ip_summed = CHECKSUM_NONE;

qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
qword = le64_to_cpu(rx_desc->qw1);
ptype = FIELD_GET(IAVF_RXD_QW1_PTYPE_MASK, qword);

decoded = libie_rx_pt_parse(ptype);
Expand Down Expand Up @@ -967,7 +966,7 @@ static void iavf_rx_checksum(struct iavf_vsi *vsi,
* @rx_ptype: Rx packet type
**/
static void iavf_rx_hash(struct iavf_ring *ring,
union iavf_rx_desc *rx_desc,
struct iavf_rx_desc *rx_desc,
struct sk_buff *skb,
u8 rx_ptype)
{
Expand All @@ -981,8 +980,8 @@ static void iavf_rx_hash(struct iavf_ring *ring,
if (!libeth_rx_pt_has_hash(ring->netdev, decoded))
return;

if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
if ((rx_desc->qw1 & rss_mask) == rss_mask) {
hash = le64_get_bits(rx_desc->qw0, IAVF_RXD_LEGACY_RSS_M);
libeth_rx_pt_set_hash(skb, hash, decoded);
}
}
Expand All @@ -1000,7 +999,7 @@ static void iavf_rx_hash(struct iavf_ring *ring,
**/
static void
iavf_process_skb_fields(struct iavf_ring *rx_ring,
union iavf_rx_desc *rx_desc, struct sk_buff *skb,
struct iavf_rx_desc *rx_desc, struct sk_buff *skb,
u8 rx_ptype)
{
iavf_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
Expand Down Expand Up @@ -1101,7 +1100,7 @@ static struct sk_buff *iavf_build_skb(const struct libeth_fqe *rx_buffer,
* that this is in fact a non-EOP buffer.
**/
static bool iavf_is_non_eop(struct iavf_ring *rx_ring,
union iavf_rx_desc *rx_desc,
struct iavf_rx_desc *rx_desc,
struct sk_buff *skb)
{
u32 ntc = rx_ring->next_to_clean + 1;
Expand Down Expand Up @@ -1143,11 +1142,12 @@ static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget)

while (likely(total_rx_packets < (unsigned int)budget)) {
struct libeth_fqe *rx_buffer;
union iavf_rx_desc *rx_desc;
struct iavf_rx_desc *rx_desc;
u16 ext_status = 0;
unsigned int size;
u16 vlan_tag = 0;
u8 rx_ptype;
u64 qword;
u64 qw1;

/* return some buffers to hardware, one at a time is too slow */
if (cleaned_count >= IAVF_RX_BUFFER_WRITE) {
Expand All @@ -1163,7 +1163,7 @@ static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget)
* which is always zero because packet split isn't used, if the
* hardware wrote DD then the length will be non-zero
*/
qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
qw1 = le64_to_cpu(rx_desc->qw1);

/* This memory barrier is needed to keep us from reading
* any other fields out of the rx_desc until we have
Expand All @@ -1174,7 +1174,7 @@ static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget)
if (!iavf_test_staterr(rx_desc, IAVF_RXD_DD))
break;

size = FIELD_GET(IAVF_RXD_QW1_LENGTH_PBUF_MASK, qword);
size = FIELD_GET(IAVF_RXD_QW1_LENGTH_PBUF_MASK, qw1);

iavf_trace(clean_rx_irq, rx_ring, rx_desc, skb);

Expand Down Expand Up @@ -1219,19 +1219,23 @@ static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget)
/* probably a little skewed due to removing CRC */
total_rx_bytes += skb->len;

qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
rx_ptype = FIELD_GET(IAVF_RXD_QW1_PTYPE_MASK, qword);
rx_ptype = FIELD_GET(IAVF_RXD_QW1_PTYPE_MASK, qw1);

/* populate checksum, VLAN, and protocol */
iavf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);

if (qword & BIT(IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT) &&
if (qw1 & BIT(IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT) &&
rx_ring->flags & IAVF_TXRX_FLAGS_VLAN_TAG_LOC_L2TAG1)
vlan_tag = le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1);
if (rx_desc->wb.qword2.ext_status &
cpu_to_le16(BIT(IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) &&
rx_ring->flags & IAVF_RXR_FLAGS_VLAN_TAG_LOC_L2TAG2_2)
vlan_tag = le16_to_cpu(rx_desc->wb.qword2.l2tag2_2);
vlan_tag = le64_get_bits(rx_desc->qw0,
IAVF_RXD_LEGACY_L2TAG1_M);

ext_status = le64_get_bits(rx_desc->qw2,
IAVF_RXD_LEGACY_EXT_STATUS_M);

if ((ext_status & IAVF_RX_DESC_EXT_STATUS_L2TAG2P_M) &&
(rx_ring->flags & IAVF_RXR_FLAGS_VLAN_TAG_LOC_L2TAG2_2))
vlan_tag = le64_get_bits(rx_desc->qw2,
IAVF_RXD_LEGACY_L2TAG2_2_M);

iavf_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
iavf_receive_skb(rx_ring, skb, vlan_tag);
Expand Down
7 changes: 2 additions & 5 deletions drivers/net/ethernet/intel/iavf/iavf_txrx.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,8 +80,6 @@ enum iavf_dyn_idx_t {
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))

#define iavf_rx_desc iavf_32byte_rx_desc

/**
* iavf_test_staterr - tests bits in Rx descriptor status and error fields
* @rx_desc: pointer to receive descriptor (in le64 format)
Expand All @@ -92,11 +90,10 @@ enum iavf_dyn_idx_t {
* The status_error_len doesn't need to be shifted because it begins
* at offset zero.
*/
static inline bool iavf_test_staterr(union iavf_rx_desc *rx_desc,
static inline bool iavf_test_staterr(struct iavf_rx_desc *rx_desc,
const u64 stat_err_bits)
{
return !!(rx_desc->wb.qword1.status_error_len &
cpu_to_le64(stat_err_bits));
return !!(rx_desc->qw1 & cpu_to_le64(stat_err_bits));
}

/* How many Rx Buffers do we bundle into one write to the hardware ? */
Expand Down
117 changes: 41 additions & 76 deletions drivers/net/ethernet/intel/iavf/iavf_type.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -178,82 +178,45 @@ struct iavf_hw {
char err_str[16];
};

/* RX Descriptors */
union iavf_16byte_rx_desc {
struct {
__le64 pkt_addr; /* Packet buffer address */
__le64 hdr_addr; /* Header buffer address */
} read;
struct {
struct {
struct {
union {
__le16 mirroring_status;
__le16 fcoe_ctx_id;
} mirr_fcoe;
__le16 l2tag1;
} lo_dword;
union {
__le32 rss; /* RSS Hash */
__le32 fd_id; /* Flow director filter id */
__le32 fcoe_param; /* FCoE DDP Context id */
} hi_dword;
} qword0;
struct {
/* ext status/error/pktype/length */
__le64 status_error_len;
} qword1;
} wb; /* writeback */
};

union iavf_32byte_rx_desc {
struct {
__le64 pkt_addr; /* Packet buffer address */
__le64 hdr_addr; /* Header buffer address */
/* bit 0 of hdr_buffer_addr is DD bit */
__le64 rsvd1;
__le64 rsvd2;
} read;
struct {
struct {
struct {
union {
__le16 mirroring_status;
__le16 fcoe_ctx_id;
} mirr_fcoe;
__le16 l2tag1;
} lo_dword;
union {
__le32 rss; /* RSS Hash */
__le32 fcoe_param; /* FCoE DDP Context id */
/* Flow director filter id in case of
* Programming status desc WB
*/
__le32 fd_id;
} hi_dword;
} qword0;
struct {
/* status/error/pktype/length */
__le64 status_error_len;
} qword1;
struct {
__le16 ext_status; /* extended status */
__le16 rsvd;
__le16 l2tag2_1;
__le16 l2tag2_2;
} qword2;
struct {
union {
__le32 flex_bytes_lo;
__le32 pe_status;
} lo_dword;
union {
__le32 flex_bytes_hi;
__le32 fd_id;
} hi_dword;
} qword3;
} wb; /* writeback */
};
/**
* struct iavf_rx_desc - Receive descriptor (both legacy and flexible)
* @qw0: quad word 0 fields:
* Legacy: Descriptor Type; Mirror ID; L2TAG1P (S-TAG); Filter Status
* Flex: Descriptor Type; Mirror ID; UMBCAST; Packet Type; Flexible Flags
* Section 0; Packet Length; Header Length; Split Header Flag;
* Flexible Flags section 1 / Extended Status
* @qw1: quad word 1 fields:
* Legacy: Status Field; Error Field; Packet Type; Packet Length (packet,
* header, Split Header Flag)
* Flex: Status / Error 0 Field; L2TAG1P (S-TAG); Flexible Metadata
* Container #0; Flexible Metadata Container #1
* @qw2: quad word 2 fields:
* Legacy: Extended Status; 1st L2TAG2P (C-TAG); 2nd L2TAG2P (C-TAG)
* Flex: Status / Error 1 Field; Flexible Flags section 2; Timestamp Low;
* 1st L2TAG2 (C-TAG); 2nd L2TAG2 (C-TAG)
* @qw3: quad word 3 fields:
* Legacy: FD Filter ID / Flexible Bytes
* Flex: Flexible Metadata Container #2; Flexible Metadata Container #3;
* Flexible Metadata Container #4 / Timestamp High 0; Flexible
* Metadata Container #5 / Timestamp High 1;
*/
struct iavf_rx_desc {
aligned_le64 qw0;
/* The hash signature (RSS) */
#define IAVF_RXD_LEGACY_RSS_M GENMASK_ULL(63, 32)
/* Stripped C-TAG VLAN from the receive packet */
#define IAVF_RXD_LEGACY_L2TAG1_M GENMASK_ULL(33, 16)

aligned_le64 qw1;
aligned_le64 qw2;
/* Stripped S-TAG VLAN from the receive packet */
#define IAVF_RXD_LEGACY_L2TAG2_2_M GENMASK_ULL(63, 48)
/* Extended status bits */
#define IAVF_RXD_LEGACY_EXT_STATUS_M GENMASK_ULL(11, 0)

aligned_le64 qw3;
} __aligned(4 * sizeof(__le64));
static_assert(sizeof(struct iavf_rx_desc) == 32);

enum iavf_rx_desc_status_bits {
/* Note: These are predefined bit offsets */
Expand Down Expand Up @@ -347,6 +310,8 @@ enum iavf_rx_desc_ext_status_bits {
IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
};

#define IAVF_RX_DESC_EXT_STATUS_L2TAG2P_M BIT(IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)

enum iavf_rx_desc_pe_status_bits {
/* Note: These are predefined bit offsets */
IAVF_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
Expand Down

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