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clk: meson8b: clean up pll clocks
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Remove the pll registration function and helpers. Replace unnecessary
configuration struct with static initialization of the desired clock
type.

Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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Michael Turquette committed Jun 23, 2016
1 parent e92f7cc commit ec623f2
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Showing 4 changed files with 131 additions and 114 deletions.
72 changes: 11 additions & 61 deletions drivers/clk/meson/clk-pll.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,13 +44,6 @@
#define MESON_PLL_RESET BIT(29)
#define MESON_PLL_LOCK BIT(31)

struct meson_clk_pll {
struct clk_hw hw;
void __iomem *base;
struct pll_conf *conf;
unsigned int rate_count;
spinlock_t *lock;
};
#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)

static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
Expand All @@ -63,15 +56,15 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
u16 n, m, od;
u32 reg;

p = &pll->conf->n;
p = &pll->n;
reg = readl(pll->base + p->reg_off);
n = PARM_GET(p->width, p->shift, reg);

p = &pll->conf->m;
p = &pll->m;
reg = readl(pll->base + p->reg_off);
m = PARM_GET(p->width, p->shift, reg);

p = &pll->conf->od;
p = &pll->od;
reg = readl(pll->base + p->reg_off);
od = PARM_GET(p->width, p->shift, reg);

Expand All @@ -84,7 +77,7 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct meson_clk_pll *pll = to_meson_clk_pll(hw);
const struct pll_rate_table *rate_table = pll->conf->rate_table;
const struct pll_rate_table *rate_table = pll->rate_table;
int i;

for (i = 0; i < pll->rate_count; i++) {
Expand All @@ -99,7 +92,7 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_pll *pll,
unsigned long rate)
{
const struct pll_rate_table *rate_table = pll->conf->rate_table;
const struct pll_rate_table *rate_table = pll->rate_table;
int i;

for (i = 0; i < pll->rate_count; i++) {
Expand Down Expand Up @@ -145,24 +138,24 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return -EINVAL;

/* PLL reset */
p = &pll->conf->n;
p = &pll->n;
reg = readl(pll->base + p->reg_off);
writel(reg | MESON_PLL_RESET, pll->base + p->reg_off);

reg = PARM_SET(p->width, p->shift, reg, rate_set->n);
writel(reg, pll->base + p->reg_off);

p = &pll->conf->m;
p = &pll->m;
reg = readl(pll->base + p->reg_off);
reg = PARM_SET(p->width, p->shift, reg, rate_set->m);
writel(reg, pll->base + p->reg_off);

p = &pll->conf->od;
p = &pll->od;
reg = readl(pll->base + p->reg_off);
reg = PARM_SET(p->width, p->shift, reg, rate_set->od);
writel(reg, pll->base + p->reg_off);

p = &pll->conf->n;
p = &pll->n;
ret = meson_clk_pll_wait_lock(pll, p);
if (ret) {
pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
Expand All @@ -173,55 +166,12 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return ret;
}

static const struct clk_ops meson_clk_pll_ops = {
const struct clk_ops meson_clk_pll_ops = {
.recalc_rate = meson_clk_pll_recalc_rate,
.round_rate = meson_clk_pll_round_rate,
.set_rate = meson_clk_pll_set_rate,
};

static const struct clk_ops meson_clk_pll_ro_ops = {
const struct clk_ops meson_clk_pll_ro_ops = {
.recalc_rate = meson_clk_pll_recalc_rate,
};

struct clk *meson_clk_register_pll(const struct clk_conf *clk_conf,
void __iomem *reg_base,
spinlock_t *lock)
{
struct clk *clk;
struct meson_clk_pll *clk_pll;
struct clk_init_data init;

clk_pll = kzalloc(sizeof(*clk_pll), GFP_KERNEL);
if (!clk_pll)
return ERR_PTR(-ENOMEM);

clk_pll->base = reg_base + clk_conf->reg_off;
clk_pll->lock = lock;
clk_pll->conf = clk_conf->conf.pll;

init.name = clk_conf->clk_name;
init.flags = clk_conf->flags | CLK_GET_RATE_NOCACHE;

init.parent_names = &clk_conf->clks_parent[0];
init.num_parents = 1;
init.ops = &meson_clk_pll_ro_ops;

/* If no rate_table is specified we assume the PLL is read-only */
if (clk_pll->conf->rate_table) {
int len;

for (len = 0; clk_pll->conf->rate_table[len].rate != 0; )
len++;

clk_pll->rate_count = len;
init.ops = &meson_clk_pll_ops;
}

clk_pll->hw.init = &init;

clk = clk_register(NULL, &clk_pll->hw);
if (IS_ERR(clk))
kfree(clk_pll);

return clk;
}
6 changes: 1 addition & 5 deletions drivers/clk/meson/clkc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@

#include "clkc.h"

static DEFINE_SPINLOCK(clk_lock);
DEFINE_SPINLOCK(clk_lock);

static struct clk **clks;
static struct clk_onecell_data clk_data;
Expand Down Expand Up @@ -190,10 +190,6 @@ void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
clk = meson_clk_register_cpu(clk_conf, clk_base,
&clk_lock);
break;
case CLK_PLL:
clk = meson_clk_register_pll(clk_conf, clk_base,
&clk_lock);
break;
default:
clk = NULL;
}
Expand Down
52 changes: 25 additions & 27 deletions drivers/clk/meson/clkc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,12 +34,13 @@ struct parm {
u8 shift;
u8 width;
};
#define PARM(_r, _s, _w) \
{ \
.reg_off = (_r), \
.shift = (_s), \
.width = (_w), \
} \

#define PARM(_r, _s, _w) \
{ \
.reg_off = (_r), \
.shift = (_s), \
.width = (_w), \
} \

struct pll_rate_table {
unsigned long rate;
Expand All @@ -55,13 +56,19 @@ struct pll_rate_table {
.od = (_od), \
} \

struct pll_conf {
const struct pll_rate_table *rate_table;
struct parm m;
struct parm n;
struct parm od;
struct meson_clk_pll {
struct clk_hw hw;
void __iomem *base;
struct parm m;
struct parm n;
struct parm od;
const struct pll_rate_table *rate_table;
unsigned int rate_count;
spinlock_t *lock;
};

#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)

struct fixed_fact_conf {
unsigned int div;
unsigned int mult;
Expand All @@ -86,7 +93,6 @@ enum clk_type {
CLK_FIXED_FACTOR,
CLK_COMPOSITE,
CLK_CPU,
CLK_PLL,
};

struct clk_conf {
Expand All @@ -100,23 +106,10 @@ struct clk_conf {
union {
struct fixed_fact_conf fixed_fact;
const struct composite_conf *composite;
struct pll_conf *pll;
const struct clk_div_table *div_table;
} conf;
};

#define PLL(_ro, _ci, _cn, _cp, _f, _c) \
{ \
.reg_off = (_ro), \
.clk_type = CLK_PLL, \
.clk_id = (_ci), \
.clk_name = (_cn), \
.clks_parent = (_cp), \
.num_parents = ARRAY_SIZE(_cp), \
.flags = (_f), \
.conf.pll = (_c), \
} \

#define FIXED_FACTOR_DIV(_ci, _cn, _cp, _f, _d) \
{ \
.clk_type = CLK_FIXED_FACTOR, \
Expand Down Expand Up @@ -155,7 +148,12 @@ void meson_clk_register_clks(const struct clk_conf *clk_confs,
unsigned int nr_confs, void __iomem *clk_base);
struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
void __iomem *reg_base, spinlock_t *lock);
struct clk *meson_clk_register_pll(const struct clk_conf *clk_conf,
void __iomem *reg_base, spinlock_t *lock);

/* shared data */
extern spinlock_t clk_lock;

/* clk_ops */
extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;

#endif /* __CLKC_H */
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