-
Notifications
You must be signed in to change notification settings - Fork 0
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/lin…
…ux into drm-next This time around we have a mix of new hw enablement (mdp5 v1.3 / apq8084), plus devicetree and various upstream changes (mostly adapting to CCF vs downstream clk driver differences) for mdp4 / apq8064. With these drm/msm patches plus a few other small patchsets (from linaro qcom integration branch.. mostly stuff queued up for 3.17) we have the inforce ifc6410 board working, with gpu. Much nicer to work with than ancient vendor android branch :-) * 'msm-next' of git://people.freedesktop.org/~robclark/linux: drm/msm/hdmi: fix HDMI_MUX_EN gpio request typo drm/msm/hdmi: enable lpm-mux if it is present drm/msm/mdp5: add support for MDP5 v1.3 drm/msm: fix potential deadlock in gpu init drm/msm: use upstream iommu drm/msm: no mmu is only error if not using vram carveout drm/msm: fix BUG_ON() in error cleanup path drm/msm/mdp4: add mdp axi clk drm/msm: hdmi phy 8960 phy pll drm/msm: update generated headers drm/msm: DT support for 8960/8064 (v3) drm/msm: Implement msm drm fb_mmap callback function drm/msm: activate iommu support drm/msm: fix double struct_mutex acquire
- Loading branch information
Showing
33 changed files
with
1,837 additions
and
392 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,52 @@ | ||
| Qualcomm adreno/snapdragon GPU | ||
|
|
||
| Required properties: | ||
| - compatible: "qcom,adreno-3xx" | ||
| - reg: Physical base address and length of the controller's registers. | ||
| - interrupts: The interrupt signal from the gpu. | ||
| - clocks: device clocks | ||
| See ../clocks/clock-bindings.txt for details. | ||
| - clock-names: the following clocks are required: | ||
| * "core_clk" | ||
| * "iface_clk" | ||
| * "mem_iface_clk" | ||
| - qcom,chipid: gpu chip-id. Note this may become optional for future | ||
| devices if we can reliably read the chipid from hw | ||
| - qcom,gpu-pwrlevels: list of operating points | ||
| - compatible: "qcom,gpu-pwrlevels" | ||
| - for each qcom,gpu-pwrlevel: | ||
| - qcom,gpu-freq: requested gpu clock speed | ||
| - NOTE: downstream android driver defines additional parameters to | ||
| configure memory bandwidth scaling per OPP. | ||
|
|
||
| Example: | ||
|
|
||
| / { | ||
| ... | ||
|
|
||
| gpu: qcom,kgsl-3d0@4300000 { | ||
| compatible = "qcom,adreno-3xx"; | ||
| reg = <0x04300000 0x20000>; | ||
| reg-names = "kgsl_3d0_reg_memory"; | ||
| interrupts = <GIC_SPI 80 0>; | ||
| interrupt-names = "kgsl_3d0_irq"; | ||
| clock-names = | ||
| "core_clk", | ||
| "iface_clk", | ||
| "mem_iface_clk"; | ||
| clocks = | ||
| <&mmcc GFX3D_CLK>, | ||
| <&mmcc GFX3D_AHB_CLK>, | ||
| <&mmcc MMSS_IMEM_AHB_CLK>; | ||
| qcom,chipid = <0x03020100>; | ||
| qcom,gpu-pwrlevels { | ||
| compatible = "qcom,gpu-pwrlevels"; | ||
| qcom,gpu-pwrlevel@0 { | ||
| qcom,gpu-freq = <450000000>; | ||
| }; | ||
| qcom,gpu-pwrlevel@1 { | ||
| qcom,gpu-freq = <27000000>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,46 @@ | ||
| Qualcomm adreno/snapdragon hdmi output | ||
|
|
||
| Required properties: | ||
| - compatible: one of the following | ||
| * "qcom,hdmi-tx-8660" | ||
| * "qcom,hdmi-tx-8960" | ||
| - reg: Physical base address and length of the controller's registers | ||
| - reg-names: "core_physical" | ||
| - interrupts: The interrupt signal from the hdmi block. | ||
| - clocks: device clocks | ||
| See ../clocks/clock-bindings.txt for details. | ||
| - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin | ||
| - qcom,hdmi-tx-ddc-data-gpio: ddc data pin | ||
| - qcom,hdmi-tx-hpd-gpio: hpd pin | ||
| - core-vdda-supply: phandle to supply regulator | ||
| - hdmi-mux-supply: phandle to mux regulator | ||
|
|
||
| Optional properties: | ||
| - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin | ||
| - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin | ||
|
|
||
| Example: | ||
|
|
||
| / { | ||
| ... | ||
|
|
||
| hdmi: qcom,hdmi-tx-8960@4a00000 { | ||
| compatible = "qcom,hdmi-tx-8960"; | ||
| reg-names = "core_physical"; | ||
| reg = <0x04a00000 0x1000>; | ||
| interrupts = <GIC_SPI 79 0>; | ||
| clock-names = | ||
| "core_clk", | ||
| "master_iface_clk", | ||
| "slave_iface_clk"; | ||
| clocks = | ||
| <&mmcc HDMI_APP_CLK>, | ||
| <&mmcc HDMI_M_AHB_CLK>, | ||
| <&mmcc HDMI_S_AHB_CLK>; | ||
| qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; | ||
| qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; | ||
| qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; | ||
| core-vdda-supply = <&pm8921_hdmi_mvs>; | ||
| hdmi-mux-supply = <&ext_3p3v>; | ||
| }; | ||
| }; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,48 @@ | ||
| Qualcomm adreno/snapdragon display controller | ||
|
|
||
| Required properties: | ||
| - compatible: | ||
| * "qcom,mdp" - mdp4 | ||
| - reg: Physical base address and length of the controller's registers. | ||
| - interrupts: The interrupt signal from the display controller. | ||
| - connectors: array of phandles for output device(s) | ||
| - clocks: device clocks | ||
| See ../clocks/clock-bindings.txt for details. | ||
| - clock-names: the following clocks are required: | ||
| * "core_clk" | ||
| * "iface_clk" | ||
| * "lut_clk" | ||
| * "src_clk" | ||
| * "hdmi_clk" | ||
| * "mpd_clk" | ||
|
|
||
| Optional properties: | ||
| - gpus: phandle for gpu device | ||
|
|
||
| Example: | ||
|
|
||
| / { | ||
| ... | ||
|
|
||
| mdp: qcom,mdp@5100000 { | ||
| compatible = "qcom,mdp"; | ||
| reg = <0x05100000 0xf0000>; | ||
| interrupts = <GIC_SPI 75 0>; | ||
| connectors = <&hdmi>; | ||
| gpus = <&gpu>; | ||
| clock-names = | ||
| "core_clk", | ||
| "iface_clk", | ||
| "lut_clk", | ||
| "src_clk", | ||
| "hdmi_clk", | ||
| "mdp_clk"; | ||
| clocks = | ||
| <&mmcc MDP_SRC>, | ||
| <&mmcc MDP_AHB_CLK>, | ||
| <&mmcc MDP_LUT_CLK>, | ||
| <&mmcc TV_SRC>, | ||
| <&mmcc HDMI_TV_CLK>, | ||
| <&mmcc MDP_TV_CLK>; | ||
| }; | ||
| }; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Oops, something went wrong.