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Documentation: Add documentation for the APM X-Gene SoC EDAC DTS binding
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Add documentation for the APM X-Gene SoC EDAC DTS binding.

Signed-off-by: Loc Ho <lho@apm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org
Cc: dougthompson@xmission.com
Cc: ijc+devicetree@hellion.org.uk
Cc: jcm@redhat.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mark.rutland@arm.com
Cc: mchehab@osg.samsung.com
Cc: patches@apm.com
Cc: robh+dt@kernel.org
Link: http://lkml.kernel.org/r/1432337580-3750-4-git-send-email-lho@apm.com
Signed-off-by: Borislav Petkov <bp@suse.de>
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Loc Ho authored and Borislav Petkov committed May 29, 2015
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78 changes: 78 additions & 0 deletions Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
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* APM X-Gene SoC EDAC node

EDAC node is defined to describe on-chip error detection and correction.
The follow error types are supported:

memory controller - Memory controller
PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache

The following section describes the EDAC DT node binding.

Required properties:
- compatible : Shall be "apm,xgene-edac".
- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
- regmap-efuse : Regmap of the PMD efuse resource.
- reg : First resource shall be the CPU bus (PCP) resource.
- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
IRQ(s).

Required properties for memory controller subnode:
- compatible : Shall be "apm,xgene-edac-mc".
- reg : First resource shall be the memory controller unit
(MCU) resource.
- memory-controller : Instance number of the memory controller.

Required properties for PMD subnode:
- compatible : Shall be "apm,xgene-edac-pmd".
- reg : First resource shall be the PMD resource.
- pmd-controller : Instance number of the PMD controller.

Example:
csw: csw@7e200000 {
compatible = "apm,xgene-csw", "syscon";
reg = <0x0 0x7e200000 0x0 0x1000>;
};

mcba: mcba@7e700000 {
compatible = "apm,xgene-mcb", "syscon";
reg = <0x0 0x7e700000 0x0 0x1000>;
};

mcbb: mcbb@7e720000 {
compatible = "apm,xgene-mcb", "syscon";
reg = <0x0 0x7e720000 0x0 0x1000>;
};

efuse: efuse@1054a000 {
compatible = "apm,xgene-efuse", "syscon";
reg = <0x0 0x1054a000 0x0 0x20>;
};

edac@78800000 {
compatible = "apm,xgene-edac";
#address-cells = <2>;
#size-cells = <2>;
ranges;
regmap-csw = <&csw>;
regmap-mcba = <&mcba>;
regmap-mcbb = <&mcbb>;
regmap-efuse = <&efuse>;
reg = <0x0 0x78800000 0x0 0x100>;
interrupts = <0x0 0x20 0x4>,
<0x0 0x21 0x4>,
<0x0 0x27 0x4>;

edacmc@7e800000 {
compatible = "apm,xgene-edac-mc";
reg = <0x0 0x7e800000 0x0 0x1000>;
memory-controller = <0>;
};

edacpmd@7c000000 {
compatible = "apm,xgene-edac-pmd";
reg = <0x0 0x7c000000 0x0 0x200000>;
pmd-controller = <0>;
};
};

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