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dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding
Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433 variant). Based on the text dt-binding posted by Jaehoon Chung. Link: https://lore.kernel.org/r/20201113170139.29956-3-m.szyprowski@samsung.com Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
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Marek Szyprowski
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Lorenzo Pieralisi
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Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Samsung SoC series PCIe Host Controller Device Tree Bindings | ||
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maintainers: | ||
- Marek Szyprowski <m.szyprowski@samsung.com> | ||
- Jaehoon Chung <jh80.chung@samsung.com> | ||
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description: |+ | ||
Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare | ||
PCIe IP and thus inherits all the common properties defined in | ||
designware-pcie.txt. | ||
allOf: | ||
- $ref: /schemas/pci/pci-bus.yaml# | ||
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properties: | ||
compatible: | ||
const: samsung,exynos5433-pcie | ||
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reg: | ||
items: | ||
- description: Data Bus Interface (DBI) registers. | ||
- description: External Local Bus interface (ELBI) registers. | ||
- description: PCIe configuration space region. | ||
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reg-names: | ||
items: | ||
- const: dbi | ||
- const: elbi | ||
- const: config | ||
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interrupts: | ||
maxItems: 1 | ||
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clocks: | ||
items: | ||
- description: PCIe bridge clock | ||
- description: PCIe bus clock | ||
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clock-names: | ||
items: | ||
- const: pcie | ||
- const: pcie_bus | ||
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phys: | ||
maxItems: 1 | ||
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vdd10-supply: | ||
description: | ||
Phandle to a regulator that provides 1.0V power to the PCIe block. | ||
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vdd18-supply: | ||
description: | ||
Phandle to a regulator that provides 1.8V power to the PCIe block. | ||
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num-lanes: | ||
const: 1 | ||
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num-viewport: | ||
const: 3 | ||
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required: | ||
- reg | ||
- reg-names | ||
- interrupts | ||
- "#address-cells" | ||
- "#size-cells" | ||
- "#interrupt-cells" | ||
- interrupt-map | ||
- interrupt-map-mask | ||
- ranges | ||
- bus-range | ||
- device_type | ||
- num-lanes | ||
- num-viewport | ||
- clocks | ||
- clock-names | ||
- phys | ||
- vdd10-supply | ||
- vdd18-supply | ||
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unevaluatedProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/interrupt-controller/irq.h> | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
#include <dt-bindings/clock/exynos5433.h> | ||
pcie: pcie@15700000 { | ||
compatible = "samsung,exynos5433-pcie"; | ||
reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; | ||
reg-names = "dbi", "elbi", "config"; | ||
#address-cells = <3>; | ||
#size-cells = <2>; | ||
#interrupt-cells = <1>; | ||
device_type = "pci"; | ||
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; | ||
clock-names = "pcie", "pcie_bus"; | ||
phys = <&pcie_phy>; | ||
pinctrl-0 = <&pcie_bus &pcie_wlanen>; | ||
pinctrl-names = "default"; | ||
num-lanes = <1>; | ||
num-viewport = <3>; | ||
bus-range = <0x00 0xff>; | ||
ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, | ||
<0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; | ||
vdd10-supply = <&ldo6_reg>; | ||
vdd18-supply = <&ldo7_reg>; | ||
interrupt-map-mask = <0 0 0 0>; | ||
interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; | ||
}; | ||
... |