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MIPS: Save/restore MSA context around signals
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This patch extends sigcontext in order to hold the most significant 64
bits of each vector register in addition to the MSA control & status
register. The least significant 64 bits are already saved as the scalar
FP context. This makes things a little awkward since the least & most
significant 64 bits of each vector register are not contiguous in
memory. Thus the copy_u & insert instructions are used to transfer the
values of the most significant 64 bits via GP registers.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6533/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored and Ralf Baechle committed Mar 26, 2014
1 parent a8ad136 commit eec43a2
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Showing 6 changed files with 357 additions and 16 deletions.
2 changes: 2 additions & 0 deletions arch/mips/include/asm/sigcontext.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,8 @@ struct sigcontext32 {
__u32 sc_lo2;
__u32 sc_hi3;
__u32 sc_lo3;
__u64 sc_msaregs[32]; /* Most significant 64 bits */
__u32 sc_msa_csr;
};
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
#endif /* _ASM_SIGCONTEXT_H */
8 changes: 8 additions & 0 deletions arch/mips/include/uapi/asm/sigcontext.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,10 @@
#include <linux/types.h>
#include <asm/sgidefs.h>

/* Bits which may be set in sc_used_math */
#define USEDMATH_FP (1 << 0)
#define USEDMATH_MSA (1 << 1)

#if _MIPS_SIM == _MIPS_SIM_ABI32

/*
Expand All @@ -37,6 +41,8 @@ struct sigcontext {
unsigned long sc_lo2;
unsigned long sc_hi3;
unsigned long sc_lo3;
unsigned long long sc_msaregs[32]; /* Most significant 64 bits */
unsigned long sc_msa_csr;
};

#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
Expand Down Expand Up @@ -70,6 +76,8 @@ struct sigcontext {
__u32 sc_used_math;
__u32 sc_dsp;
__u32 sc_reserved;
__u64 sc_msaregs[32];
__u32 sc_msa_csr;
};


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3 changes: 3 additions & 0 deletions arch/mips/kernel/asm-offsets.c
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Original file line number Diff line number Diff line change
Expand Up @@ -295,6 +295,7 @@ void output_sc_defines(void)
OFFSET(SC_LO2, sigcontext, sc_lo2);
OFFSET(SC_HI3, sigcontext, sc_hi3);
OFFSET(SC_LO3, sigcontext, sc_lo3);
OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
BLANK();
}
#endif
Expand All @@ -309,6 +310,7 @@ void output_sc_defines(void)
OFFSET(SC_MDLO, sigcontext, sc_mdlo);
OFFSET(SC_PC, sigcontext, sc_pc);
OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
BLANK();
}
#endif
Expand All @@ -320,6 +322,7 @@ void output_sc32_defines(void)
OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs);
BLANK();
}
#endif
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213 changes: 213 additions & 0 deletions arch/mips/kernel/r4k_fpu.S
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
* Copyright (C) 1999, 2001 Silicon Graphics, Inc.
*/
#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/errno.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
Expand Down Expand Up @@ -245,6 +246,218 @@ LEAF(_restore_fp_context32)
END(_restore_fp_context32)
#endif

#ifdef CONFIG_CPU_HAS_MSA

.macro save_sc_msareg wr, off, sc, tmp
#ifdef CONFIG_64BIT
copy_u_d \tmp, \wr, 1
EX sd \tmp, (\off+(\wr*8))(\sc)
#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
copy_u_w \tmp, \wr, 2
EX sw \tmp, (\off+(\wr*8)+0)(\sc)
copy_u_w \tmp, \wr, 3
EX sw \tmp, (\off+(\wr*8)+4)(\sc)
#else /* CONFIG_CPU_BIG_ENDIAN */
copy_u_w \tmp, \wr, 2
EX sw \tmp, (\off+(\wr*8)+4)(\sc)
copy_u_w \tmp, \wr, 3
EX sw \tmp, (\off+(\wr*8)+0)(\sc)
#endif
.endm

/*
* int _save_msa_context(struct sigcontext *sc)
*
* Save the upper 64 bits of each vector register along with the MSA_CSR
* register into sc. Returns zero on success, else non-zero.
*/
LEAF(_save_msa_context)
save_sc_msareg 0, SC_MSAREGS, a0, t0
save_sc_msareg 1, SC_MSAREGS, a0, t0
save_sc_msareg 2, SC_MSAREGS, a0, t0
save_sc_msareg 3, SC_MSAREGS, a0, t0
save_sc_msareg 4, SC_MSAREGS, a0, t0
save_sc_msareg 5, SC_MSAREGS, a0, t0
save_sc_msareg 6, SC_MSAREGS, a0, t0
save_sc_msareg 7, SC_MSAREGS, a0, t0
save_sc_msareg 8, SC_MSAREGS, a0, t0
save_sc_msareg 9, SC_MSAREGS, a0, t0
save_sc_msareg 10, SC_MSAREGS, a0, t0
save_sc_msareg 11, SC_MSAREGS, a0, t0
save_sc_msareg 12, SC_MSAREGS, a0, t0
save_sc_msareg 13, SC_MSAREGS, a0, t0
save_sc_msareg 14, SC_MSAREGS, a0, t0
save_sc_msareg 15, SC_MSAREGS, a0, t0
save_sc_msareg 16, SC_MSAREGS, a0, t0
save_sc_msareg 17, SC_MSAREGS, a0, t0
save_sc_msareg 18, SC_MSAREGS, a0, t0
save_sc_msareg 19, SC_MSAREGS, a0, t0
save_sc_msareg 20, SC_MSAREGS, a0, t0
save_sc_msareg 21, SC_MSAREGS, a0, t0
save_sc_msareg 22, SC_MSAREGS, a0, t0
save_sc_msareg 23, SC_MSAREGS, a0, t0
save_sc_msareg 24, SC_MSAREGS, a0, t0
save_sc_msareg 25, SC_MSAREGS, a0, t0
save_sc_msareg 26, SC_MSAREGS, a0, t0
save_sc_msareg 27, SC_MSAREGS, a0, t0
save_sc_msareg 28, SC_MSAREGS, a0, t0
save_sc_msareg 29, SC_MSAREGS, a0, t0
save_sc_msareg 30, SC_MSAREGS, a0, t0
save_sc_msareg 31, SC_MSAREGS, a0, t0
jr ra
li v0, 0
END(_save_msa_context)

#ifdef CONFIG_MIPS32_COMPAT

/*
* int _save_msa_context32(struct sigcontext32 *sc)
*
* Save the upper 64 bits of each vector register along with the MSA_CSR
* register into sc. Returns zero on success, else non-zero.
*/
LEAF(_save_msa_context32)
save_sc_msareg 0, SC32_MSAREGS, a0, t0
save_sc_msareg 1, SC32_MSAREGS, a0, t0
save_sc_msareg 2, SC32_MSAREGS, a0, t0
save_sc_msareg 3, SC32_MSAREGS, a0, t0
save_sc_msareg 4, SC32_MSAREGS, a0, t0
save_sc_msareg 5, SC32_MSAREGS, a0, t0
save_sc_msareg 6, SC32_MSAREGS, a0, t0
save_sc_msareg 7, SC32_MSAREGS, a0, t0
save_sc_msareg 8, SC32_MSAREGS, a0, t0
save_sc_msareg 9, SC32_MSAREGS, a0, t0
save_sc_msareg 10, SC32_MSAREGS, a0, t0
save_sc_msareg 11, SC32_MSAREGS, a0, t0
save_sc_msareg 12, SC32_MSAREGS, a0, t0
save_sc_msareg 13, SC32_MSAREGS, a0, t0
save_sc_msareg 14, SC32_MSAREGS, a0, t0
save_sc_msareg 15, SC32_MSAREGS, a0, t0
save_sc_msareg 16, SC32_MSAREGS, a0, t0
save_sc_msareg 17, SC32_MSAREGS, a0, t0
save_sc_msareg 18, SC32_MSAREGS, a0, t0
save_sc_msareg 19, SC32_MSAREGS, a0, t0
save_sc_msareg 20, SC32_MSAREGS, a0, t0
save_sc_msareg 21, SC32_MSAREGS, a0, t0
save_sc_msareg 22, SC32_MSAREGS, a0, t0
save_sc_msareg 23, SC32_MSAREGS, a0, t0
save_sc_msareg 24, SC32_MSAREGS, a0, t0
save_sc_msareg 25, SC32_MSAREGS, a0, t0
save_sc_msareg 26, SC32_MSAREGS, a0, t0
save_sc_msareg 27, SC32_MSAREGS, a0, t0
save_sc_msareg 28, SC32_MSAREGS, a0, t0
save_sc_msareg 29, SC32_MSAREGS, a0, t0
save_sc_msareg 30, SC32_MSAREGS, a0, t0
save_sc_msareg 31, SC32_MSAREGS, a0, t0
jr ra
li v0, 0
END(_save_msa_context32)

#endif /* CONFIG_MIPS32_COMPAT */

.macro restore_sc_msareg wr, off, sc, tmp
#ifdef CONFIG_64BIT
EX ld \tmp, (\off+(\wr*8))(\sc)
insert_d \wr, 1, \tmp
#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
EX lw \tmp, (\off+(\wr*8)+0)(\sc)
insert_w \wr, 2, \tmp
EX lw \tmp, (\off+(\wr*8)+4)(\sc)
insert_w \wr, 3, \tmp
#else /* CONFIG_CPU_BIG_ENDIAN */
EX lw \tmp, (\off+(\wr*8)+4)(\sc)
insert_w \wr, 2, \tmp
EX lw \tmp, (\off+(\wr*8)+0)(\sc)
insert_w \wr, 3, \tmp
#endif
.endm

/*
* int _restore_msa_context(struct sigcontext *sc)
*/
LEAF(_restore_msa_context)
restore_sc_msareg 0, SC_MSAREGS, a0, t0
restore_sc_msareg 1, SC_MSAREGS, a0, t0
restore_sc_msareg 2, SC_MSAREGS, a0, t0
restore_sc_msareg 3, SC_MSAREGS, a0, t0
restore_sc_msareg 4, SC_MSAREGS, a0, t0
restore_sc_msareg 5, SC_MSAREGS, a0, t0
restore_sc_msareg 6, SC_MSAREGS, a0, t0
restore_sc_msareg 7, SC_MSAREGS, a0, t0
restore_sc_msareg 8, SC_MSAREGS, a0, t0
restore_sc_msareg 9, SC_MSAREGS, a0, t0
restore_sc_msareg 10, SC_MSAREGS, a0, t0
restore_sc_msareg 11, SC_MSAREGS, a0, t0
restore_sc_msareg 12, SC_MSAREGS, a0, t0
restore_sc_msareg 13, SC_MSAREGS, a0, t0
restore_sc_msareg 14, SC_MSAREGS, a0, t0
restore_sc_msareg 15, SC_MSAREGS, a0, t0
restore_sc_msareg 16, SC_MSAREGS, a0, t0
restore_sc_msareg 17, SC_MSAREGS, a0, t0
restore_sc_msareg 18, SC_MSAREGS, a0, t0
restore_sc_msareg 19, SC_MSAREGS, a0, t0
restore_sc_msareg 20, SC_MSAREGS, a0, t0
restore_sc_msareg 21, SC_MSAREGS, a0, t0
restore_sc_msareg 22, SC_MSAREGS, a0, t0
restore_sc_msareg 23, SC_MSAREGS, a0, t0
restore_sc_msareg 24, SC_MSAREGS, a0, t0
restore_sc_msareg 25, SC_MSAREGS, a0, t0
restore_sc_msareg 26, SC_MSAREGS, a0, t0
restore_sc_msareg 27, SC_MSAREGS, a0, t0
restore_sc_msareg 28, SC_MSAREGS, a0, t0
restore_sc_msareg 29, SC_MSAREGS, a0, t0
restore_sc_msareg 30, SC_MSAREGS, a0, t0
restore_sc_msareg 31, SC_MSAREGS, a0, t0
jr ra
li v0, 0
END(_restore_msa_context)

#ifdef CONFIG_MIPS32_COMPAT

/*
* int _restore_msa_context32(struct sigcontext32 *sc)
*/
LEAF(_restore_msa_context32)
restore_sc_msareg 0, SC32_MSAREGS, a0, t0
restore_sc_msareg 1, SC32_MSAREGS, a0, t0
restore_sc_msareg 2, SC32_MSAREGS, a0, t0
restore_sc_msareg 3, SC32_MSAREGS, a0, t0
restore_sc_msareg 4, SC32_MSAREGS, a0, t0
restore_sc_msareg 5, SC32_MSAREGS, a0, t0
restore_sc_msareg 6, SC32_MSAREGS, a0, t0
restore_sc_msareg 7, SC32_MSAREGS, a0, t0
restore_sc_msareg 8, SC32_MSAREGS, a0, t0
restore_sc_msareg 9, SC32_MSAREGS, a0, t0
restore_sc_msareg 10, SC32_MSAREGS, a0, t0
restore_sc_msareg 11, SC32_MSAREGS, a0, t0
restore_sc_msareg 12, SC32_MSAREGS, a0, t0
restore_sc_msareg 13, SC32_MSAREGS, a0, t0
restore_sc_msareg 14, SC32_MSAREGS, a0, t0
restore_sc_msareg 15, SC32_MSAREGS, a0, t0
restore_sc_msareg 16, SC32_MSAREGS, a0, t0
restore_sc_msareg 17, SC32_MSAREGS, a0, t0
restore_sc_msareg 18, SC32_MSAREGS, a0, t0
restore_sc_msareg 19, SC32_MSAREGS, a0, t0
restore_sc_msareg 20, SC32_MSAREGS, a0, t0
restore_sc_msareg 21, SC32_MSAREGS, a0, t0
restore_sc_msareg 22, SC32_MSAREGS, a0, t0
restore_sc_msareg 23, SC32_MSAREGS, a0, t0
restore_sc_msareg 24, SC32_MSAREGS, a0, t0
restore_sc_msareg 25, SC32_MSAREGS, a0, t0
restore_sc_msareg 26, SC32_MSAREGS, a0, t0
restore_sc_msareg 27, SC32_MSAREGS, a0, t0
restore_sc_msareg 28, SC32_MSAREGS, a0, t0
restore_sc_msareg 29, SC32_MSAREGS, a0, t0
restore_sc_msareg 30, SC32_MSAREGS, a0, t0
restore_sc_msareg 31, SC32_MSAREGS, a0, t0
jr ra
li v0, 0
END(_restore_msa_context32)

#endif /* CONFIG_MIPS32_COMPAT */

#endif /* CONFIG_CPU_HAS_MSA */

.set reorder

.type fault@function
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