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cxgb4: add data structures to support vxlan
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Add data structures and macros to be used in vxlan
offload.

Original work by: Santosh Rastapur <santosh@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Ganesh Goudar authored and David S. Miller committed Jan 11, 2018
1 parent c5e62a2 commit ef0fd85
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164 changes: 164 additions & 0 deletions drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -107,6 +107,7 @@ enum {

CPL_FW6_MSG = 0xE0,
CPL_FW6_PLD = 0xE1,
CPL_TX_TNL_LSO = 0xEC,
CPL_TX_PKT_LSO = 0xED,
CPL_TX_PKT_XT = 0xEE,

Expand Down Expand Up @@ -1479,6 +1480,169 @@ struct ulp_txpkt {
#define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
#define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)

enum cpl_tx_tnl_lso_type {
TX_TNL_TYPE_OPAQUE,
TX_TNL_TYPE_NVGRE,
TX_TNL_TYPE_VXLAN,
TX_TNL_TYPE_GENEVE,
};

struct cpl_tx_tnl_lso {
__be32 op_to_IpIdSplitOut;
__be16 IpIdOffsetOut;
__be16 UdpLenSetOut_to_TnlHdrLen;
__be64 r1;
__be32 Flow_to_TcpHdrLen;
__be16 IpIdOffset;
__be16 IpIdSplit_to_Mss;
__be32 TCPSeqOffset;
__be32 EthLenOffset_Size;
/* encapsulated CPL (TX_PKT_XT) follows here */
};

#define CPL_TX_TNL_LSO_OPCODE_S 24
#define CPL_TX_TNL_LSO_OPCODE_M 0xff
#define CPL_TX_TNL_LSO_OPCODE_V(x) ((x) << CPL_TX_TNL_LSO_OPCODE_S)
#define CPL_TX_TNL_LSO_OPCODE_G(x) \
(((x) >> CPL_TX_TNL_LSO_OPCODE_S) & CPL_TX_TNL_LSO_OPCODE_M)

#define CPL_TX_TNL_LSO_FIRST_S 23
#define CPL_TX_TNL_LSO_FIRST_M 0x1
#define CPL_TX_TNL_LSO_FIRST_V(x) ((x) << CPL_TX_TNL_LSO_FIRST_S)
#define CPL_TX_TNL_LSO_FIRST_G(x) \
(((x) >> CPL_TX_TNL_LSO_FIRST_S) & CPL_TX_TNL_LSO_FIRST_M)
#define CPL_TX_TNL_LSO_FIRST_F CPL_TX_TNL_LSO_FIRST_V(1U)

#define CPL_TX_TNL_LSO_LAST_S 22
#define CPL_TX_TNL_LSO_LAST_M 0x1
#define CPL_TX_TNL_LSO_LAST_V(x) ((x) << CPL_TX_TNL_LSO_LAST_S)
#define CPL_TX_TNL_LSO_LAST_G(x) \
(((x) >> CPL_TX_TNL_LSO_LAST_S) & CPL_TX_TNL_LSO_LAST_M)
#define CPL_TX_TNL_LSO_LAST_F CPL_TX_TNL_LSO_LAST_V(1U)

#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_S 21
#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_M 0x1
#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(x) \
((x) << CPL_TX_TNL_LSO_ETHHDRLENXOUT_S)
#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_G(x) \
(((x) >> CPL_TX_TNL_LSO_ETHHDRLENXOUT_S) & \
CPL_TX_TNL_LSO_ETHHDRLENXOUT_M)
#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_F CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(1U)

#define CPL_TX_TNL_LSO_IPV6OUT_S 20
#define CPL_TX_TNL_LSO_IPV6OUT_M 0x1
#define CPL_TX_TNL_LSO_IPV6OUT_V(x) ((x) << CPL_TX_TNL_LSO_IPV6OUT_S)
#define CPL_TX_TNL_LSO_IPV6OUT_G(x) \
(((x) >> CPL_TX_TNL_LSO_IPV6OUT_S) & CPL_TX_TNL_LSO_IPV6OUT_M)
#define CPL_TX_TNL_LSO_IPV6OUT_F CPL_TX_TNL_LSO_IPV6OUT_V(1U)

#define CPL_TX_TNL_LSO_ETHHDRLEN_S 16
#define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf
#define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S)
#define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \
(((x) >> CPL_TX_TNL_LSO_ETHHDRLEN_S) & CPL_TX_TNL_LSO_ETHHDRLEN_M)

#define CPL_TX_TNL_LSO_IPHDRLEN_S 4
#define CPL_TX_TNL_LSO_IPHDRLEN_M 0xfff
#define CPL_TX_TNL_LSO_IPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLEN_S)
#define CPL_TX_TNL_LSO_IPHDRLEN_G(x) \
(((x) >> CPL_TX_TNL_LSO_IPHDRLEN_S) & CPL_TX_TNL_LSO_IPHDRLEN_M)

#define CPL_TX_TNL_LSO_TCPHDRLEN_S 0
#define CPL_TX_TNL_LSO_TCPHDRLEN_M 0xf
#define CPL_TX_TNL_LSO_TCPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TCPHDRLEN_S)
#define CPL_TX_TNL_LSO_TCPHDRLEN_G(x) \
(((x) >> CPL_TX_TNL_LSO_TCPHDRLEN_S) & CPL_TX_TNL_LSO_TCPHDRLEN_M)

#define CPL_TX_TNL_LSO_MSS_S 0
#define CPL_TX_TNL_LSO_MSS_M 0x3fff
#define CPL_TX_TNL_LSO_MSS_V(x) ((x) << CPL_TX_TNL_LSO_MSS_S)
#define CPL_TX_TNL_LSO_MSS_G(x) \
(((x) >> CPL_TX_TNL_LSO_MSS_S) & CPL_TX_TNL_LSO_MSS_M)

#define CPL_TX_TNL_LSO_SIZE_S 0
#define CPL_TX_TNL_LSO_SIZE_M 0xfffffff
#define CPL_TX_TNL_LSO_SIZE_V(x) ((x) << CPL_TX_TNL_LSO_SIZE_S)
#define CPL_TX_TNL_LSO_SIZE_G(x) \
(((x) >> CPL_TX_TNL_LSO_SIZE_S) & CPL_TX_TNL_LSO_SIZE_M)

#define CPL_TX_TNL_LSO_ETHHDRLENOUT_S 16
#define CPL_TX_TNL_LSO_ETHHDRLENOUT_M 0xf
#define CPL_TX_TNL_LSO_ETHHDRLENOUT_V(x) \
((x) << CPL_TX_TNL_LSO_ETHHDRLENOUT_S)
#define CPL_TX_TNL_LSO_ETHHDRLENOUT_G(x) \
(((x) >> CPL_TX_TNL_LSO_ETHHDRLENOUT_S) & CPL_TX_TNL_LSO_ETHHDRLENOUT_M)

#define CPL_TX_TNL_LSO_IPHDRLENOUT_S 4
#define CPL_TX_TNL_LSO_IPHDRLENOUT_M 0xfff
#define CPL_TX_TNL_LSO_IPHDRLENOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLENOUT_S)
#define CPL_TX_TNL_LSO_IPHDRLENOUT_G(x) \
(((x) >> CPL_TX_TNL_LSO_IPHDRLENOUT_S) & CPL_TX_TNL_LSO_IPHDRLENOUT_M)

#define CPL_TX_TNL_LSO_IPHDRCHKOUT_S 3
#define CPL_TX_TNL_LSO_IPHDRCHKOUT_M 0x1
#define CPL_TX_TNL_LSO_IPHDRCHKOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRCHKOUT_S)
#define CPL_TX_TNL_LSO_IPHDRCHKOUT_G(x) \
(((x) >> CPL_TX_TNL_LSO_IPHDRCHKOUT_S) & CPL_TX_TNL_LSO_IPHDRCHKOUT_M)
#define CPL_TX_TNL_LSO_IPHDRCHKOUT_F CPL_TX_TNL_LSO_IPHDRCHKOUT_V(1U)

#define CPL_TX_TNL_LSO_IPLENSETOUT_S 2
#define CPL_TX_TNL_LSO_IPLENSETOUT_M 0x1
#define CPL_TX_TNL_LSO_IPLENSETOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPLENSETOUT_S)
#define CPL_TX_TNL_LSO_IPLENSETOUT_G(x) \
(((x) >> CPL_TX_TNL_LSO_IPLENSETOUT_S) & CPL_TX_TNL_LSO_IPLENSETOUT_M)
#define CPL_TX_TNL_LSO_IPLENSETOUT_F CPL_TX_TNL_LSO_IPLENSETOUT_V(1U)

#define CPL_TX_TNL_LSO_IPIDINCOUT_S 1
#define CPL_TX_TNL_LSO_IPIDINCOUT_M 0x1
#define CPL_TX_TNL_LSO_IPIDINCOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPIDINCOUT_S)
#define CPL_TX_TNL_LSO_IPIDINCOUT_G(x) \
(((x) >> CPL_TX_TNL_LSO_IPIDINCOUT_S) & CPL_TX_TNL_LSO_IPIDINCOUT_M)
#define CPL_TX_TNL_LSO_IPIDINCOUT_F CPL_TX_TNL_LSO_IPIDINCOUT_V(1U)

#define CPL_TX_TNL_LSO_UDPCHKCLROUT_S 14
#define CPL_TX_TNL_LSO_UDPCHKCLROUT_M 0x1
#define CPL_TX_TNL_LSO_UDPCHKCLROUT_V(x) \
((x) << CPL_TX_TNL_LSO_UDPCHKCLROUT_S)
#define CPL_TX_TNL_LSO_UDPCHKCLROUT_G(x) \
(((x) >> CPL_TX_TNL_LSO_UDPCHKCLROUT_S) & \
CPL_TX_TNL_LSO_UDPCHKCLROUT_M)
#define CPL_TX_TNL_LSO_UDPCHKCLROUT_F CPL_TX_TNL_LSO_UDPCHKCLROUT_V(1U)

#define CPL_TX_TNL_LSO_UDPLENSETOUT_S 15
#define CPL_TX_TNL_LSO_UDPLENSETOUT_M 0x1
#define CPL_TX_TNL_LSO_UDPLENSETOUT_V(x) \
((x) << CPL_TX_TNL_LSO_UDPLENSETOUT_S)
#define CPL_TX_TNL_LSO_UDPLENSETOUT_G(x) \
(((x) >> CPL_TX_TNL_LSO_UDPLENSETOUT_S) & \
CPL_TX_TNL_LSO_UDPLENSETOUT_M)
#define CPL_TX_TNL_LSO_UDPLENSETOUT_F CPL_TX_TNL_LSO_UDPLENSETOUT_V(1U)

#define CPL_TX_TNL_LSO_TNLTYPE_S 12
#define CPL_TX_TNL_LSO_TNLTYPE_M 0x3
#define CPL_TX_TNL_LSO_TNLTYPE_V(x) ((x) << CPL_TX_TNL_LSO_TNLTYPE_S)
#define CPL_TX_TNL_LSO_TNLTYPE_G(x) \
(((x) >> CPL_TX_TNL_LSO_TNLTYPE_S) & CPL_TX_TNL_LSO_TNLTYPE_M)

#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16
#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf
#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
(((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)

#define CPL_TX_TNL_LSO_TNLHDRLEN_S 0
#define CPL_TX_TNL_LSO_TNLHDRLEN_M 0xfff
#define CPL_TX_TNL_LSO_TNLHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TNLHDRLEN_S)
#define CPL_TX_TNL_LSO_TNLHDRLEN_G(x) \
(((x) >> CPL_TX_TNL_LSO_TNLHDRLEN_S) & CPL_TX_TNL_LSO_TNLHDRLEN_M)

#define CPL_TX_TNL_LSO_IPV6_S 20
#define CPL_TX_TNL_LSO_IPV6_M 0x1
#define CPL_TX_TNL_LSO_IPV6_V(x) ((x) << CPL_TX_TNL_LSO_IPV6_S)
#define CPL_TX_TNL_LSO_IPV6_G(x) \
(((x) >> CPL_TX_TNL_LSO_IPV6_S) & CPL_TX_TNL_LSO_IPV6_M)
#define CPL_TX_TNL_LSO_IPV6_F CPL_TX_TNL_LSO_IPV6_V(1U)

#define ULP_TX_SC_MORE_S 23
#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
#define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
Expand Down
17 changes: 17 additions & 0 deletions drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2511,6 +2511,17 @@
#define MPS_RX_MAC_BG_PG_CNT0_A 0x11208
#define MPS_RX_LPBK_BG_PG_CNT0_A 0x11218

#define MPS_RX_VXLAN_TYPE_A 0x11234

#define VXLAN_EN_S 16
#define VXLAN_EN_V(x) ((x) << VXLAN_EN_S)
#define VXLAN_EN_F VXLAN_EN_V(1U)

#define VXLAN_S 0
#define VXLAN_M 0xffffU
#define VXLAN_V(x) ((x) << VXLAN_S)
#define VXLAN_G(x) (((x) >> VXLAN_S) & VXLAN_M)

#define MPS_CLS_TCAM_Y_L_A 0xf000
#define MPS_CLS_TCAM_DATA0_A 0xf000
#define MPS_CLS_TCAM_DATA1_A 0xf004
Expand All @@ -2537,8 +2548,14 @@

#define DATAPORTNUM_S 12
#define DATAPORTNUM_M 0xfU
#define DATAPORTNUM_V(x) ((x) << DATAPORTNUM_S)
#define DATAPORTNUM_G(x) (((x) >> DATAPORTNUM_S) & DATAPORTNUM_M)

#define DATALKPTYPE_S 10
#define DATALKPTYPE_M 0x3U
#define DATALKPTYPE_V(x) ((x) << DATALKPTYPE_S)
#define DATALKPTYPE_G(x) (((x) >> DATALKPTYPE_S) & DATALKPTYPE_M)

#define DATADIPHIT_S 8
#define DATADIPHIT_V(x) ((x) << DATADIPHIT_S)
#define DATADIPHIT_F DATADIPHIT_V(1U)
Expand Down
27 changes: 27 additions & 0 deletions drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2060,6 +2060,7 @@ struct fw_vi_cmd {
#define FW_VI_MAC_ADD_MAC 0x3FF
#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
#define FW_VI_MAC_MAC_BASED_FREE 0x3FD
#define FW_VI_MAC_ID_BASED_FREE 0x3FC
#define FW_CLS_TCAM_NUM_ENTRIES 336

enum fw_vi_mac_smac {
Expand All @@ -2076,6 +2077,13 @@ enum fw_vi_mac_result {
FW_VI_MAC_R_F_ACL_CHECK
};

enum fw_vi_mac_entry_types {
FW_VI_MAC_TYPE_EXACTMAC,
FW_VI_MAC_TYPE_HASHVEC,
FW_VI_MAC_TYPE_RAW,
FW_VI_MAC_TYPE_EXACTMAC_VNI,
};

struct fw_vi_mac_cmd {
__be32 op_to_viid;
__be32 freemacs_to_len16;
Expand All @@ -2087,6 +2095,13 @@ struct fw_vi_mac_cmd {
struct fw_vi_mac_hash {
__be64 hashvec;
} hash;
struct fw_vi_mac_raw {
__be32 raw_idx_pkd;
__be32 data0_pkd;
__be32 data1[2];
__be64 data0m_pkd;
__be32 data1m[2];
} raw;
} u;
};

Expand All @@ -2096,6 +2111,12 @@ struct fw_vi_mac_cmd {
#define FW_VI_MAC_CMD_FREEMACS_S 31
#define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S)

#define FW_VI_MAC_CMD_ENTRY_TYPE_S 23
#define FW_VI_MAC_CMD_ENTRY_TYPE_M 0x7
#define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S)
#define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \
(((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M)

#define FW_VI_MAC_CMD_HASHVECEN_S 23
#define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
#define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U)
Expand All @@ -2122,6 +2143,12 @@ struct fw_vi_mac_cmd {
#define FW_VI_MAC_CMD_IDX_G(x) \
(((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)

#define FW_VI_MAC_CMD_RAW_IDX_S 16
#define FW_VI_MAC_CMD_RAW_IDX_M 0xffff
#define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S)
#define FW_VI_MAC_CMD_RAW_IDX_G(x) \
(((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M)

#define FW_RXMODE_MTU_NO_CHG 65535

struct fw_vi_rxmode_cmd {
Expand Down

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