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cxgb4/cxgb4vf/csiostor: Cleanup SGE and PCI related register defines
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This patch cleansup remaining SGE related macros/register defines and all PCI
related ones that are defined in t4_regs.h and the affected files.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Hariprasad Shenai authored and David S. Miller committed Jan 5, 2015
1 parent f612b81 commit f061de4
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Showing 13 changed files with 766 additions and 532 deletions.
68 changes: 34 additions & 34 deletions drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1590,9 +1590,9 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
data += sizeof(struct queue_port_stats) / sizeof(u64);
if (!is_t4(adapter->params.chip)) {
t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7));
val1 = t4_read_reg(adapter, SGE_STAT_TOTAL_A);
val2 = t4_read_reg(adapter, SGE_STAT_MATCH_A);
*data = val1 - val2;
data++;
*data = val2;
Expand Down Expand Up @@ -3601,14 +3601,14 @@ unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
struct adapter *adap = netdev2adap(dev);
u32 v1, v2, lp_count, hp_count;

v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
if (is_t4(adap->params.chip)) {
lp_count = G_LP_COUNT(v1);
hp_count = G_HP_COUNT(v1);
lp_count = LP_COUNT_G(v1);
hp_count = HP_COUNT_G(v1);
} else {
lp_count = G_LP_COUNT_T5(v1);
hp_count = G_HP_COUNT_T5(v2);
lp_count = LP_COUNT_T5_G(v1);
hp_count = HP_COUNT_T5_G(v2);
}
return lpfifo ? lp_count : hp_count;
}
Expand Down Expand Up @@ -3667,14 +3667,14 @@ int cxgb4_flush_eq_cache(struct net_device *dev)
int ret;

ret = t4_fwaddrspace_write(adap, adap->mbox,
0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
0xe1000000 + SGE_CTXT_CMD_A, 0x20000000);
return ret;
}
EXPORT_SYMBOL(cxgb4_flush_eq_cache);

static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
{
u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
__be64 indices;
int ret;

Expand Down Expand Up @@ -3728,7 +3728,7 @@ void cxgb4_disable_db_coalescing(struct net_device *dev)
struct adapter *adap;

adap = netdev2adap(dev);
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F,
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F,
NOCOALESCE_F);
}
EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
Expand All @@ -3738,7 +3738,7 @@ void cxgb4_enable_db_coalescing(struct net_device *dev)
struct adapter *adap;

adap = netdev2adap(dev);
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F, 0);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F, 0);
}
EXPORT_SYMBOL(cxgb4_enable_db_coalescing);

Expand Down Expand Up @@ -3877,14 +3877,14 @@ static void drain_db_fifo(struct adapter *adap, int usecs)
u32 v1, v2, lp_count, hp_count;

do {
v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
if (is_t4(adap->params.chip)) {
lp_count = G_LP_COUNT(v1);
hp_count = G_HP_COUNT(v1);
lp_count = LP_COUNT_G(v1);
hp_count = HP_COUNT_G(v1);
} else {
lp_count = G_LP_COUNT_T5(v1);
hp_count = G_HP_COUNT_T5(v2);
lp_count = LP_COUNT_T5_G(v1);
hp_count = HP_COUNT_T5_G(v2);
}

if (lp_count == 0 && hp_count == 0)
Expand Down Expand Up @@ -4044,7 +4044,7 @@ static void process_db_drop(struct work_struct *work)
t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
}

t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
}

void t4_db_full(struct adapter *adap)
Expand Down Expand Up @@ -4871,16 +4871,16 @@ static void setup_memwin(struct adapter *adap)
mem_win2_base = MEMWIN2_BASE_T5;
mem_win2_aperture = MEMWIN2_APERTURE_T5;
}
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
mem_win0_base | BIR(0) |
WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
mem_win1_base | BIR(0) |
WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
mem_win2_base | BIR(0) |
WINDOW(ilog2(mem_win2_aperture) - 10));
t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 0),
mem_win0_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN0_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 1),
mem_win1_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN1_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2),
mem_win2_base | BIR_V(0) |
WINDOW_V(ilog2(mem_win2_aperture) - 10));
t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2));
}

static void setup_memwin_rdma(struct adapter *adap)
Expand All @@ -4894,13 +4894,13 @@ static void setup_memwin_rdma(struct adapter *adap)
start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
start | BIR(1) | WINDOW(ilog2(sz_kb)));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
adap->vres.ocq.start);
t4_read_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
}
}

Expand Down
78 changes: 39 additions & 39 deletions drivers/net/ethernet/chelsio/cxgb4/sge.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2098,7 +2098,7 @@ static irqreturn_t t4_intr_intx(int irq, void *cookie)
{
struct adapter *adap = cookie;

t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI), 0);
t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
if (t4_slow_intr_handler(adap) | process_intrq(adap))
return IRQ_HANDLED;
return IRQ_NONE; /* probably shared interrupt */
Expand Down Expand Up @@ -2145,9 +2145,9 @@ static void sge_rx_timer_cb(unsigned long data)
}
}

t4_write_reg(adap, SGE_DEBUG_INDEX, 13);
idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH);
idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
t4_write_reg(adap, SGE_DEBUG_INDEX_A, 13);
idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH_A);
idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);

for (i = 0; i < 2; i++) {
u32 debug0, debug11;
Expand Down Expand Up @@ -2191,12 +2191,12 @@ static void sge_rx_timer_cb(unsigned long data)
/* Read and save the SGE IDMA State and Queue ID information.
* We do this every time in case it changes across time ...
*/
t4_write_reg(adap, SGE_DEBUG_INDEX, 0);
debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
t4_write_reg(adap, SGE_DEBUG_INDEX_A, 0);
debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;

t4_write_reg(adap, SGE_DEBUG_INDEX, 11);
debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
t4_write_reg(adap, SGE_DEBUG_INDEX_A, 11);
debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;

CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n",
Expand Down Expand Up @@ -2826,21 +2826,21 @@ static int t4_sge_init_soft(struct adapter *adap)
* Retrieve our RX interrupt holdoff timer values and counter
* threshold values from the SGE parameters.
*/
timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1);
timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3);
timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5);
timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A);
timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A);
timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A);
s->timer_val[0] = core_ticks_to_us(adap,
TIMERVALUE0_GET(timer_value_0_and_1));
TIMERVALUE0_G(timer_value_0_and_1));
s->timer_val[1] = core_ticks_to_us(adap,
TIMERVALUE1_GET(timer_value_0_and_1));
TIMERVALUE1_G(timer_value_0_and_1));
s->timer_val[2] = core_ticks_to_us(adap,
TIMERVALUE2_GET(timer_value_2_and_3));
TIMERVALUE2_G(timer_value_2_and_3));
s->timer_val[3] = core_ticks_to_us(adap,
TIMERVALUE3_GET(timer_value_2_and_3));
TIMERVALUE3_G(timer_value_2_and_3));
s->timer_val[4] = core_ticks_to_us(adap,
TIMERVALUE4_GET(timer_value_4_and_5));
TIMERVALUE4_G(timer_value_4_and_5));
s->timer_val[5] = core_ticks_to_us(adap,
TIMERVALUE5_GET(timer_value_4_and_5));
TIMERVALUE5_G(timer_value_4_and_5));

ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A);
s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
Expand All @@ -2866,21 +2866,21 @@ static int t4_sge_init_hard(struct adapter *adap)
* and generate an interrupt when this occurs so we can recover.
*/
if (is_t4(adap->params.chip)) {
t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
V_HP_INT_THRESH(M_HP_INT_THRESH) |
V_LP_INT_THRESH(M_LP_INT_THRESH),
V_HP_INT_THRESH(dbfifo_int_thresh) |
V_LP_INT_THRESH(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,
HP_INT_THRESH_V(HP_INT_THRESH_M) |
LP_INT_THRESH_V(LP_INT_THRESH_M),
HP_INT_THRESH_V(dbfifo_int_thresh) |
LP_INT_THRESH_V(dbfifo_int_thresh));
} else {
t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5),
V_LP_INT_THRESH_T5(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS2,
V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5),
V_HP_INT_THRESH_T5(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,
LP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M),
LP_INT_THRESH_T5_V(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS2_A,
HP_INT_THRESH_T5_V(HP_INT_THRESH_T5_M),
HP_INT_THRESH_T5_V(dbfifo_int_thresh));
}
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP,
F_ENABLE_DROP);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F,
ENABLE_DROP_F);

/*
* SGE_FL_BUFFER_SIZE0 (RX_SMALL_PG_BUF) is set up by
Expand All @@ -2905,15 +2905,15 @@ static int t4_sge_init_hard(struct adapter *adap)
THRESHOLD_1_V(s->counter_val[1]) |
THRESHOLD_2_V(s->counter_val[2]) |
THRESHOLD_3_V(s->counter_val[3]));
t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1,
TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) |
TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1])));
t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3,
TIMERVALUE2(us_to_core_ticks(adap, s->timer_val[2])) |
TIMERVALUE3(us_to_core_ticks(adap, s->timer_val[3])));
t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5,
TIMERVALUE4(us_to_core_ticks(adap, s->timer_val[4])) |
TIMERVALUE5(us_to_core_ticks(adap, s->timer_val[5])));
t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1_A,
TIMERVALUE0_V(us_to_core_ticks(adap, s->timer_val[0])) |
TIMERVALUE1_V(us_to_core_ticks(adap, s->timer_val[1])));
t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3_A,
TIMERVALUE2_V(us_to_core_ticks(adap, s->timer_val[2])) |
TIMERVALUE3_V(us_to_core_ticks(adap, s->timer_val[3])));
t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5_A,
TIMERVALUE4_V(us_to_core_ticks(adap, s->timer_val[4])) |
TIMERVALUE5_V(us_to_core_ticks(adap, s->timer_val[5])));

return 0;
}
Expand Down
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