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Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller is different than the older SoCs SPI controller in internal design as well as register interface. This driver supports the: - non DMA based transfer for smaller transfer i.e. less than FIFO depth. - APB DMA based transfer for larger transfer i.e. more than FIFO depth. - Clock gating through runtime PM callbacks. - registration through DT only. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Laxman Dewangan
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Grant Likely
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Apr 7, 2013
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Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
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NVIDIA Tegra114 SPI controller. | ||
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Required properties: | ||
- compatible : should be "nvidia,tegra114-spi". | ||
- reg: Should contain SPI registers location and length. | ||
- interrupts: Should contain SPI interrupts. | ||
- nvidia,dma-request-selector : The Tegra DMA controller's phandle and | ||
request selector for this SPI controller. | ||
- This is also require clock named "spi" as per binding document | ||
Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
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Recommended properties: | ||
- spi-max-frequency: Definition as per | ||
Documentation/devicetree/bindings/spi/spi-bus.txt | ||
Example: | ||
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spi@7000d600 { | ||
compatible = "nvidia,tegra114-spi"; | ||
reg = <0x7000d600 0x200>; | ||
interrupts = <0 82 0x04>; | ||
nvidia,dma-request-selector = <&apbdma 16>; | ||
spi-max-frequency = <25000000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
status = "disabled"; | ||
}; |
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