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RISC-V: KVM: Add kvm_vcpu_config
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Add a placeholder for all registers such as henvcfg, hstateen etc
which have 'static' configurations depending on extensions supported by
the guest. The values are derived once and are then subsequently written
to the corresponding CSRs while switching to the vcpu.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
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Mayuresh Chitale authored and Anup Patel committed Oct 12, 2023
1 parent 00c6f39 commit fe0bab7
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Showing 2 changed files with 21 additions and 13 deletions.
7 changes: 7 additions & 0 deletions arch/riscv/include/asm/kvm_host.h
Original file line number Diff line number Diff line change
Expand Up @@ -164,6 +164,10 @@ struct kvm_vcpu_csr {
unsigned long scounteren;
};

struct kvm_vcpu_config {
u64 henvcfg;
};

struct kvm_vcpu_arch {
/* VCPU ran at least once */
bool ran_atleast_once;
Expand Down Expand Up @@ -244,6 +248,9 @@ struct kvm_vcpu_arch {

/* Performance monitoring context */
struct kvm_pmu pmu_context;

/* 'static' configurations which are set only once */
struct kvm_vcpu_config cfg;
};

static inline void kvm_arch_sync_events(struct kvm *kvm) {}
Expand Down
27 changes: 14 additions & 13 deletions arch/riscv/kvm/vcpu.c
Original file line number Diff line number Diff line change
Expand Up @@ -471,31 +471,28 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
return -EINVAL;
}

static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
{
u64 henvcfg = 0;
const unsigned long *isa = vcpu->arch.isa;
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;

if (riscv_isa_extension_available(isa, SVPBMT))
henvcfg |= ENVCFG_PBMTE;
cfg->henvcfg |= ENVCFG_PBMTE;

if (riscv_isa_extension_available(isa, SSTC))
henvcfg |= ENVCFG_STCE;
cfg->henvcfg |= ENVCFG_STCE;

if (riscv_isa_extension_available(isa, ZICBOM))
henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
cfg->henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);

if (riscv_isa_extension_available(isa, ZICBOZ))
henvcfg |= ENVCFG_CBZE;

csr_write(CSR_HENVCFG, henvcfg);
#ifdef CONFIG_32BIT
csr_write(CSR_HENVCFGH, henvcfg >> 32);
#endif
cfg->henvcfg |= ENVCFG_CBZE;
}

void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
{
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;

csr_write(CSR_VSSTATUS, csr->vsstatus);
csr_write(CSR_VSIE, csr->vsie);
Expand All @@ -506,8 +503,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
csr_write(CSR_VSTVAL, csr->vstval);
csr_write(CSR_HVIP, csr->hvip);
csr_write(CSR_VSATP, csr->vsatp);

kvm_riscv_vcpu_update_config(vcpu->arch.isa);
csr_write(CSR_HENVCFG, cfg->henvcfg);
if (IS_ENABLED(CONFIG_32BIT))
csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32);

kvm_riscv_gstage_update_hgatp(vcpu);

Expand Down Expand Up @@ -627,6 +625,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
struct kvm_cpu_trap trap;
struct kvm_run *run = vcpu->run;

if (!vcpu->arch.ran_atleast_once)
kvm_riscv_vcpu_setup_config(vcpu);

/* Mark this VCPU ran at least once */
vcpu->arch.ran_atleast_once = true;

Expand Down

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