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ARM: dts: qcom: sdx55: Add USB3 and PHY support
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Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and
SNPS HS PHY on SDX55.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210118051005.55958-3-manivannan.sadhasivam@linaro.org
[bjorn: Added missing #power-domain-cells to &gcc]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Manivannan Sadhasivam authored and Bjorn Andersson committed Jan 22, 2021
1 parent 0e43e08 commit fea4b41
Showing 1 changed file with 86 additions and 0 deletions.
86 changes: 86 additions & 0 deletions arch/arm/boot/dts/qcom-sdx55.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -130,6 +130,7 @@
reg = <0x100000 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "bi_tcxo", "sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
};
Expand All @@ -144,6 +145,48 @@
status = "disabled";
};

usb_hsphy: phy@ff4000 {
compatible = "qcom,usb-snps-hs-7nm-phy";
reg = <0x00ff4000 0x114>;
status = "disabled";
#phy-cells = <0>;

clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";

resets = <&gcc GCC_QUSB2PHY_BCR>;
};

usb_qmpphy: phy@ff6000 {
compatible = "qcom,sdx55-qmp-usb3-uni-phy";
reg = <0x00ff6000 0x1c0>;
status = "disabled";
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;

clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";

resets = <&gcc GCC_USB3PHY_PHY_BCR>,
<&gcc GCC_USB3_PHY_BCR>;
reset-names = "phy", "common";

usb_ssphy: phy@ff6200 {
reg = <0x00ff6200 0x170>,
<0x00ff6400 0x200>,
<0x00ff6800 0x800>;
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_uni_phy_pipe_clk_src";
};
};

qpic_bam: dma-controller@1b04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x01b04000 0x1c000>;
Expand Down Expand Up @@ -190,6 +233,49 @@
status = "disabled";
};

usb: usb@a6f8800 {
compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
reg = <0x0a6f8800 0x400>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges;

clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_USB30_MSTR_AXI_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep";

assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;

interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";

power-domains = <&gcc USB30_GDSC>;

resets = <&gcc GCC_USB30_BCR>;

usb_dwc3: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0x0a600000 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x1a0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_hsphy>, <&usb_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};

pdc: interrupt-controller@b210000 {
compatible = "qcom,sdx55-pdc", "qcom,pdc";
reg = <0x0b210000 0x30000>;
Expand Down

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