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* pm-cpufreq: (51 commits) Documentation: intel_pstate: Document HWP energy/performance hints cpufreq: intel_pstate: Support for energy performance hints with HWP cpufreq: intel_pstate: Add locking around HWP requests cpufreq: ondemand: Set MIN_FREQUENCY_UP_THRESHOLD to 1 cpufreq: intel_pstate: Add Knights Mill CPUID MAINTAINERS: Add bug tracking system location entry for cpufreq cpufreq: dt: Add support for zx296718 cpufreq: acpi-cpufreq: drop rdmsr_on_cpus() usage cpufreq: acpi-cpufreq: Convert to hotplug state machine cpufreq: intel_pstate: fix intel_pstate_exit_perf_limits() prototype cpufreq: intel_pstate: Set EPP/EPB to 0 in performance mode cpufreq: schedutil: Rectify comment in sugov_irq_work() function cpufreq: intel_pstate: increase precision of performance limits cpufreq: intel_pstate: round up min_perf limits cpufreq: Make cpufreq_update_policy() void ACPI / processor: Make acpi_processor_ppc_has_changed() void cpufreq: Avoid using inactive policies cpufreq: intel_pstate: Generic governors support cpufreq: intel_pstate: Request P-states control from SMM if needed cpufreq: dt: Add support for r8a7743 and r8a7745 ...
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Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
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Original file line number | Diff line number | Diff line change |
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Broadcom AVS mail box and interrupt register bindings | ||
===================================================== | ||
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A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem) | ||
references the mailbox register used to communicate with the AVS CPU[1]. The | ||
second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on | ||
the AVS CPU. The interrupt tells the AVS CPU that it needs to process a | ||
command sent to it by a driver. Interrupting the AVS CPU is mandatory for | ||
commands to be processed. | ||
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The interface also requires a reference to the AVS host interrupt controller, | ||
so a driver can react to interrupts generated by the AVS CPU whenever a command | ||
has been processed. See [2] for more information on the brcm,l2-intc node. | ||
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[1] The AVS CPU is an independent co-processor that runs proprietary | ||
firmware. On some SoCs, this firmware supports DFS and DVFS in addition to | ||
Adaptive Voltage Scaling. | ||
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[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt | ||
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Node brcm,avs-cpu-data-mem | ||
-------------------------- | ||
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Required properties: | ||
- compatible: must include: brcm,avs-cpu-data-mem and | ||
should include: one of brcm,bcm7271-avs-cpu-data-mem or | ||
brcm,bcm7268-avs-cpu-data-mem | ||
- reg: Specifies base physical address and size of the registers. | ||
- interrupts: The interrupt that the AVS CPU will use to interrupt the host | ||
when a command completed. | ||
- interrupt-parent: The interrupt controller the above interrupt is routed | ||
through. | ||
- interrupt-names: The name of the interrupt used to interrupt the host. | ||
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Optional properties: | ||
- None | ||
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Node brcm,avs-cpu-l2-intr | ||
------------------------- | ||
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Required properties: | ||
- compatible: must include: brcm,avs-cpu-l2-intr and | ||
should include: one of brcm,bcm7271-avs-cpu-l2-intr or | ||
brcm,bcm7268-avs-cpu-l2-intr | ||
- reg: Specifies base physical address and size of the registers. | ||
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Optional properties: | ||
- None | ||
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Example | ||
======= | ||
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avs_host_l2_intc: interrupt-controller@f04d1200 { | ||
#interrupt-cells = <1>; | ||
compatible = "brcm,l2-intc"; | ||
interrupt-parent = <&intc>; | ||
reg = <0xf04d1200 0x48>; | ||
interrupt-controller; | ||
interrupts = <0x0 0x19 0x0>; | ||
interrupt-names = "avs"; | ||
}; | ||
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avs-cpu-data-mem@f04c4000 { | ||
compatible = "brcm,bcm7271-avs-cpu-data-mem", | ||
"brcm,avs-cpu-data-mem"; | ||
reg = <0xf04c4000 0x60>; | ||
interrupts = <0x1a>; | ||
interrupt-parent = <&avs_host_l2_intc>; | ||
interrupt-names = "sw_intr"; | ||
}; | ||
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avs-cpu-l2-intr@f04d1100 { | ||
compatible = "brcm,bcm7271-avs-cpu-l2-intr", | ||
"brcm,avs-cpu-l2-intr"; | ||
reg = <0xf04d1100 0x10>; | ||
}; |
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