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Merge branch 'hns3-cleanups'
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Guangbin Huang says:

====================
hns3: some cleanups for -next

To improve code readability and simplicity, this series refactor some
functions in the HNS3 ethernet driver.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
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David S. Miller committed Nov 29, 2021
2 parents aeeecb8 + 1d851c0 commit ff45b48
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Showing 8 changed files with 431 additions and 354 deletions.
434 changes: 240 additions & 194 deletions drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
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5 changes: 5 additions & 0 deletions drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
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Original file line number Diff line number Diff line change
Expand Up @@ -621,6 +621,11 @@ static inline int ring_space(struct hns3_enet_ring *ring)
(begin - end)) - 1;
}

static inline u32 hns3_tqp_read_reg(struct hns3_enet_ring *ring, u32 reg)
{
return readl_relaxed(ring->tqp->io_base + reg);
}

static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
{
return readl(base + reg);
Expand Down
93 changes: 43 additions & 50 deletions drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -258,12 +258,29 @@ hclge_dbg_dump_reg_common(struct hclge_dev *hdev,
return 0;
}

static const struct hclge_dbg_status_dfx_info hclge_dbg_mac_en_status[] = {
{HCLGE_MAC_TX_EN_B, "mac_trans_en"},
{HCLGE_MAC_RX_EN_B, "mac_rcv_en"},
{HCLGE_MAC_PAD_TX_B, "pad_trans_en"},
{HCLGE_MAC_PAD_RX_B, "pad_rcv_en"},
{HCLGE_MAC_1588_TX_B, "1588_trans_en"},
{HCLGE_MAC_1588_RX_B, "1588_rcv_en"},
{HCLGE_MAC_APP_LP_B, "mac_app_loop_en"},
{HCLGE_MAC_LINE_LP_B, "mac_line_loop_en"},
{HCLGE_MAC_FCS_TX_B, "mac_fcs_tx_en"},
{HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, "mac_rx_oversize_truncate_en"},
{HCLGE_MAC_RX_FCS_STRIP_B, "mac_rx_fcs_strip_en"},
{HCLGE_MAC_RX_FCS_B, "mac_rx_fcs_en"},
{HCLGE_MAC_TX_UNDER_MIN_ERR_B, "mac_tx_under_min_err_en"},
{HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, "mac_tx_oversize_truncate_en"}
};

static int hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev, char *buf,
int len, int *pos)
{
struct hclge_config_mac_mode_cmd *req;
struct hclge_desc desc;
u32 loop_en;
u32 loop_en, i, offset;
int ret;

hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
Expand All @@ -278,39 +295,12 @@ static int hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev, char *buf,
req = (struct hclge_config_mac_mode_cmd *)desc.data;
loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);

*pos += scnprintf(buf + *pos, len - *pos, "mac_trans_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_TX_EN_B));
*pos += scnprintf(buf + *pos, len - *pos, "mac_rcv_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_RX_EN_B));
*pos += scnprintf(buf + *pos, len - *pos, "pad_trans_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_PAD_TX_B));
*pos += scnprintf(buf + *pos, len - *pos, "pad_rcv_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_PAD_RX_B));
*pos += scnprintf(buf + *pos, len - *pos, "1588_trans_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_1588_TX_B));
*pos += scnprintf(buf + *pos, len - *pos, "1588_rcv_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_1588_RX_B));
*pos += scnprintf(buf + *pos, len - *pos, "mac_app_loop_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_APP_LP_B));
*pos += scnprintf(buf + *pos, len - *pos, "mac_line_loop_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_LINE_LP_B));
*pos += scnprintf(buf + *pos, len - *pos, "mac_fcs_tx_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_FCS_TX_B));
*pos += scnprintf(buf + *pos, len - *pos,
"mac_rx_oversize_truncate_en: %#x\n",
hnae3_get_bit(loop_en,
HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B));
*pos += scnprintf(buf + *pos, len - *pos, "mac_rx_fcs_strip_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B));
*pos += scnprintf(buf + *pos, len - *pos, "mac_rx_fcs_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_RX_FCS_B));
*pos += scnprintf(buf + *pos, len - *pos,
"mac_tx_under_min_err_en: %#x\n",
hnae3_get_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B));
*pos += scnprintf(buf + *pos, len - *pos,
"mac_tx_oversize_truncate_en: %#x\n",
hnae3_get_bit(loop_en,
HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B));
for (i = 0; i < ARRAY_SIZE(hclge_dbg_mac_en_status); i++) {
offset = hclge_dbg_mac_en_status[i].offset;
*pos += scnprintf(buf + *pos, len - *pos, "%s: %#x\n",
hclge_dbg_mac_en_status[i].message,
hnae3_get_bit(loop_en, offset));
}

return 0;
}
Expand Down Expand Up @@ -1614,8 +1604,19 @@ static int hclge_dbg_dump_fd_counter(struct hclge_dev *hdev, char *buf, int len)
return 0;
}

static const struct hclge_dbg_status_dfx_info hclge_dbg_rst_info[] = {
{HCLGE_MISC_VECTOR_REG_BASE, "vector0 interrupt enable status"},
{HCLGE_MISC_RESET_STS_REG, "reset interrupt source"},
{HCLGE_MISC_VECTOR_INT_STS, "reset interrupt status"},
{HCLGE_RAS_PF_OTHER_INT_STS_REG, "RAS interrupt status"},
{HCLGE_GLOBAL_RESET_REG, "hardware reset status"},
{HCLGE_NIC_CSQ_DEPTH_REG, "handshake status"},
{HCLGE_FUN_RST_ING, "function reset status"}
};

int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len)
{
u32 i, offset;
int pos = 0;

pos += scnprintf(buf + pos, len - pos, "PF reset count: %u\n",
Expand All @@ -1634,22 +1635,14 @@ int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len)
hdev->rst_stats.reset_cnt);
pos += scnprintf(buf + pos, len - pos, "reset fail count: %u\n",
hdev->rst_stats.reset_fail_cnt);
pos += scnprintf(buf + pos, len - pos,
"vector0 interrupt enable status: 0x%x\n",
hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_REG_BASE));
pos += scnprintf(buf + pos, len - pos, "reset interrupt source: 0x%x\n",
hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG));
pos += scnprintf(buf + pos, len - pos, "reset interrupt status: 0x%x\n",
hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS));
pos += scnprintf(buf + pos, len - pos, "RAS interrupt status: 0x%x\n",
hclge_read_dev(&hdev->hw,
HCLGE_RAS_PF_OTHER_INT_STS_REG));
pos += scnprintf(buf + pos, len - pos, "hardware reset status: 0x%x\n",
hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG));
pos += scnprintf(buf + pos, len - pos, "handshake status: 0x%x\n",
hclge_read_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG));
pos += scnprintf(buf + pos, len - pos, "function reset status: 0x%x\n",
hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING));

for (i = 0; i < ARRAY_SIZE(hclge_dbg_rst_info); i++) {
offset = hclge_dbg_rst_info[i].offset;
pos += scnprintf(buf + pos, len - pos, "%s: 0x%x\n",
hclge_dbg_rst_info[i].message,
hclge_read_dev(&hdev->hw, offset));
}

pos += scnprintf(buf + pos, len - pos, "hdev state: 0x%lx\n",
hdev->state);

Expand Down
5 changes: 5 additions & 0 deletions drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,11 @@ struct hclge_dbg_func {
char *buf, int len);
};

struct hclge_dbg_status_dfx_info {
u32 offset;
char message[HCLGE_DBG_MAX_DFX_MSG_LEN];
};

static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = {
{false, "Reserved"},
{true, "BP_CPU_STATE"},
Expand Down
103 changes: 46 additions & 57 deletions drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2653,11 +2653,38 @@ static u8 hclge_check_speed_dup(u8 duplex, int speed)
return duplex;
}

struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = {
{HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M},
{HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M},
{HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G},
{HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G},
{HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G},
{HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G},
{HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G},
{HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G},
{HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G},
};

static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw)
{
u16 i;

for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) {
if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) {
*speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw;
return 0;
}
}

return -EINVAL;
}

static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
u8 duplex)
{
struct hclge_config_mac_speed_dup_cmd *req;
struct hclge_desc desc;
u32 speed_fw;
int ret;

req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
Expand All @@ -2667,48 +2694,14 @@ static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
if (duplex)
hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1);

switch (speed) {
case HCLGE_MAC_SPEED_10M:
hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_10M);
break;
case HCLGE_MAC_SPEED_100M:
hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_100M);
break;
case HCLGE_MAC_SPEED_1G:
hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_1G);
break;
case HCLGE_MAC_SPEED_10G:
hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_10G);
break;
case HCLGE_MAC_SPEED_25G:
hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_25G);
break;
case HCLGE_MAC_SPEED_40G:
hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_40G);
break;
case HCLGE_MAC_SPEED_50G:
hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_50G);
break;
case HCLGE_MAC_SPEED_100G:
hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_100G);
break;
case HCLGE_MAC_SPEED_200G:
hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_200G);
break;
default:
ret = hclge_convert_to_fw_speed(speed, &speed_fw);
if (ret) {
dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
return -EINVAL;
return ret;
}

hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S,
speed_fw);
hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1);

Expand Down Expand Up @@ -11589,24 +11582,20 @@ static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
int retry_cnt = 0;
int ret;

retry:
down(&hdev->reset_sem);
set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
hdev->reset_type = rst_type;
ret = hclge_reset_prepare(hdev);
if (ret || hdev->reset_pending) {
dev_err(&hdev->pdev->dev, "fail to prepare to reset, ret=%d\n",
ret);
if (hdev->reset_pending ||
retry_cnt++ < HCLGE_RESET_RETRY_CNT) {
dev_err(&hdev->pdev->dev,
"reset_pending:0x%lx, retry_cnt:%d\n",
hdev->reset_pending, retry_cnt);
clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
up(&hdev->reset_sem);
msleep(HCLGE_RESET_RETRY_WAIT_MS);
goto retry;
}
while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) {
down(&hdev->reset_sem);
set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
hdev->reset_type = rst_type;
ret = hclge_reset_prepare(hdev);
if (!ret && !hdev->reset_pending)
break;

dev_err(&hdev->pdev->dev,
"failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n",
ret, hdev->reset_pending, retry_cnt);
clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
up(&hdev->reset_sem);
msleep(HCLGE_RESET_RETRY_WAIT_MS);
}

/* disable misc vector before reset done */
Expand Down
5 changes: 5 additions & 0 deletions drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1095,6 +1095,11 @@ struct hclge_speed_bit_map {
u32 speed_bit;
};

struct hclge_mac_speed_map {
u32 speed_drv; /* speed defined in driver */
u32 speed_fw; /* speed defined in firmware */
};

int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
bool en_mc_pmc, bool en_bc_pmc);
int hclge_add_uc_addr_common(struct hclge_vport *vport,
Expand Down
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