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arm64: dts: renesas: r9a07g054: Fillup the SDHI{0,1} stub nodes
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Fillup the SDHI{0,1} stub nodes in RZ/V2L (R9A07G054) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220227203744.18355-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Lad Prabhakar authored and Geert Uytterhoeven committed Apr 4, 2022
1 parent 8eb5092 commit ffe3f13
Showing 1 changed file with 24 additions and 2 deletions.
26 changes: 24 additions & 2 deletions arch/arm64/boot/dts/renesas/r9a07g054.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -398,13 +398,35 @@
};

sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g054",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
/* place holder */
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G054_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};

sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g054",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
/* place holder */
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G054_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};

eth0: ethernet@11c20000 {
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