irq-core-2020-01-28

 - A mechanism to shield isolated tasks from managed interrupts:

   The affinity of managed interrupts is completely controlled by the
   kernel and user space has no influence on them. The reason is that
   the automatically assigned affinity correlates to the multi-queue
   CPU handling of block devices.

   If the generated affinity mask spaws both housekeeping and isolated CPUs
   the interrupt could be routed to an isolated CPU which would then be
   disturbed by I/O submitted by a housekeeping CPU.

   The new mechamism ensures that as long as one housekeeping CPU is online
   in the assigned affinity mask the interrupt is routed to a housekeeping
   CPU.

   If there is no online housekeeping CPU in the affinity mask, then the
   interrupt is routed to an isolated CPU to keep the device queue intact,
   but unless the isolated CPU submits I/O by itself these interrupts are
   not raised.

 - A small addon to the device tree irqdomain core code to avoid
   duplication in irq chip drivers

 - Conversion of the SiFive PLIC to hierarchical domains

 - The usual pile of new irq chip drivers: SiFive GPIO, Aspeed SCI, NXP
   INTMUX, Meson A1 GPIO

 - The first cut of support for the new ARM GICv4.1

 - The usual pile of fixes and improvements in core and driver code