misc-habanalabs-fixes-2020-07-10

- Prevent user from using command WREG_BULK in PCI DMA channel. The command
  won't be parsed correctly by the driver and will cause unknown behavior.
  As the user doesn't need to use that command in that channel, its better
  to just prevent it completely.

- Change the interface of the clock gating debugfs property from true/false
  to bitmask with bit per engine. This will allow the user to debug the
  ASIC while disabling the clock gating feature with fine-grain
  granularity.

- Increase message-to-ASIC-CPU timeout to 4s (from 100ms/1s). The ASIC CPU
  might respond sometimes after a large delay due to slow external
  interfaces (such as temperature sensors) and that will result in a driver
  timeout which will lead to ASIC reset.