x86-cpu-2021-08-30

  A stop gap for potential future speculation related hardware
  vulnerabilities and a mechanism for truly security paranoid
  applications.

  It allows a task to request that the L1D cache is flushed when the kernel
  switches to a different mm. This can be requested via prctl().

  Changes vs. the previous versions:

    - Get rid of the software flush fallback

    - Make the handling consistent with other mitigations

    - Kill the task when it ends up on a SMT enabled core which defeats the
      purpose of L1D flushing obviously