x86-urgent-2020-12-06

 - Make the AMD L3 QoS code and data priorization enable/disable mechanism
   work correctly. The control bit was only set/cleared on one of the CPUs
   in a L3 domain, but it has to be modified on all CPUs in the domain. The
   initial documentation was not clear about this, but the updated one from
   Oct 2020 spells it out.

 - Fix an off by one in the UV platform detection code which causes the UV
   hubs to be identified wrongly. The chip revisions start at 1 not at 0.

 - Fix a long standing bug in the evaluation of prefixes in the uprobes
   code which fails to handle repeated prefixes properly. The aggregate
   size of the prefixes can be larger than the bytes array but the code
   blindly iterated over the aggregate size beyond the array boundary.
   Add a macro to handle this case properly and use it at the affected
   places.