---

yaml
---
r: 43145
b: refs/heads/master
c: d9408ce
h: refs/heads/master
i:
  43143: d86ec6b
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: b65780e123ba9b762276482bbfb52836e4d41fd9
+refs/heads/master: d9408cefe677636bc1c100fdcfac0b2ab9ff87bf

trunk/arch/i386/kernel/smpboot.c

@@ -1130,34 +1130,15 @@ static int __cpuinit __smp_prepare_cpu(int cpu)
 }
 #endif
 
-static void smp_tune_scheduling (void)
+static void smp_tune_scheduling(void)
 {
 	unsigned long cachesize;       /* kB   */
-	unsigned long bandwidth = 350; /* MB/s */
-	/*
-	 * Rough estimation for SMP scheduling, this is the number of
-	 * cycles it takes for a fully memory-limited process to flush
-	 * the SMP-local cache.
-	 *
-	 * (For a P5 this pretty much means we will choose another idle
-	 *  CPU almost always at wakeup time (this is due to the small
-	 *  L1 cache), on PIIs it's around 50-100 usecs, depending on
-	 *  the cache size)
-	 */
 
-	if (!cpu_khz) {
-		/*
-		 * this basically disables processor-affinity
-		 * scheduling on SMP without a TSC.
-		 */
-		return;
-	} else {
+	if (cpu_khz) {
 		cachesize = boot_cpu_data.x86_cache_size;
-		if (cachesize == -1) {
-			cachesize = 16; /* Pentiums, 2x8kB cache */
-			bandwidth = 100;
-		}
-		max_cache_size = cachesize * 1024;
+
+		if (cachesize > 0)
+			max_cache_size = cachesize * 1024;
 	}
 }