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yaml --- r: 281759 b: refs/heads/master c: 1b46f87 h: refs/heads/master i: 281757: 44c5962 281755: 6a449e7 281751: c9441d1 281743: 2792d1a 281727: 0c0bbeb v: v3
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Jamie Iles
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Dec 18, 2011
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refs/heads/master: f68453e076dcf140c4a7bdd385f239b1e41be983 | ||
refs/heads/master: 1b46f8782c2607afa1298b0c7f7fe307fc0f7a5b |
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* ARM Vectored Interrupt Controller | ||
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||
One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM | ||
system for interrupt routing. For multiple controllers they can either be | ||
nested or have the outputs wire-OR'd together. | ||
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Required properties: | ||
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- compatible : should be one of | ||
"arm,pl190-vic" | ||
"arm,pl192-vic" | ||
- interrupt-controller : Identifies the node as an interrupt controller | ||
- #interrupt-cells : The number of cells to define the interrupts. Must be 1 as | ||
the VIC has no configuration options for interrupt sources. The cell is a u32 | ||
and defines the interrupt number. | ||
- reg : The register bank for the VIC. | ||
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Optional properties: | ||
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- interrupts : Interrupt source for parent controllers if the VIC is nested. | ||
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Example: | ||
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vic0: interrupt-controller@60000 { | ||
compatible = "arm,pl192-vic"; | ||
interrupt-controller; | ||
#interrupt-cells = <1>; | ||
reg = <0x60000 0x1000>; | ||
}; |
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