---

yaml --- r: 115727 b: refs/heads/master c: b612eda h: refs/heads/master i: 115725: b20b4b3 115723: fa6ed52 115719: 0556915 115711: e281c12 v: v3
git-mirror · Oct 17, 2008 · 34a9be1 · 34a9be1
1 parent de273b4
commit 34a9be1
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6dbe2772d6af067845bab57be490c302f4490ac7
+refs/heads/master: b612eda98e4b4bae4c98a863f039bc89425f9039
diff --git a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -96,7 +96,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 		 */
 		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-	} else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {
+	} else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) ||
+		   IS_GM45(dev)) {
 		uint32_t dcc;
 
 		/* On 915-945 and GM965, channel interleave by the CPU is
@@ -118,7 +119,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 			    dcc & DCC_CHANNEL_XOR_DISABLE) {
 				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 				swizzle_y = I915_BIT_6_SWIZZLE_9;
-			} else if (IS_I965GM(dev)) {
+			} else if (IS_I965GM(dev) || IS_GM45(dev)) {
 				/* GM965 only does bit 11-based channel
 				 * randomization
 				 */