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yaml --- r: 127069 b: refs/heads/master c: 94106e0 h: refs/heads/master i: 127067: d54f6c2 v: v3
git-mirror · Jan 7, 2009 · 5cce186 · 5cce186
1 parent d13e765
commit 5cce186
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diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1ea9925553caad6ea5068b4652596f149e0be9c3
+refs/heads/master: 94106e0fb6b863348a566617ca6bf431c37ddc5e
diff --git a/trunk/arch/blackfin/Kconfig b/trunk/arch/blackfin/Kconfig
@@ -866,7 +866,7 @@ endchoice
 
 config BFIN_L2_CACHEABLE
 	bool "Cache L2 SRAM"
-	depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+	depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
 	default n
 	help
 	  Select to make L2 SRAM cacheable in L1 data and instruction cache.