---

yaml
---
r: 314079
b: refs/heads/master
c: d5b5927
h: refs/heads/master
i:
  314077: b08e508
  314075: 5392cf6
  314071: 786e6d2
  314063: c1cd268
  314047: 84e2dcb
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a9c130d522ddef8673728fa9738f4f3f8e61f9b9
+refs/heads/master: d5b592764f5b21979f6260869bd96e69aa0536bb

trunk/drivers/net/wireless/ti/wl18xx/main.c

@@ -44,6 +44,12 @@
 static char *ht_mode_param;
 static char *board_type_param;
 
+static const u32 wl18xx_board_type_to_scrpad2[NUM_BOARD_TYPES] = {
+	[BOARD_TYPE_FPGA_18XX]		= SCR_PAD2_BOARD_TYPE_FPGA,
+	[BOARD_TYPE_HDK_18XX]		= SCR_PAD2_BOARD_TYPE_HDK,
+	[BOARD_TYPE_DVP_EVB_18XX]	= SCR_PAD2_BOARD_TYPE_DVP_EVB,
+};
+
 static const u8 wl18xx_rate_to_idx_2ghz[] = {
 	/* MCS rates are used only with 11n */
 	15,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
@@ -584,11 +590,11 @@ static int wl18xx_identify_chip(struct wl1271 *wl)
 
 static void wl18xx_set_clk(struct wl1271 *wl)
 {
-	/*
-	 * TODO: this is hardcoded just for DVP/EVB, fix according to
-	 * new unified_drv.
-	 */
-	wl1271_write32(wl, WL18XX_SCR_PAD2, 0xB3);
+	struct wl18xx_priv *priv = wl->priv;
+
+	/* write the translated board type to SCR_PAD2 */
+	wl1271_write32(wl, WL18XX_SCR_PAD2,
+		       wl18xx_board_type_to_scrpad2[priv->board_type]);
 
 	wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 	wl1271_write32(wl, 0x00A02360, 0xD0078);

trunk/drivers/net/wireless/ti/wl18xx/reg.h

@@ -154,6 +154,15 @@ enum {
 	BOARD_TYPE_FPGA_18XX	= 0,
 	BOARD_TYPE_HDK_18XX	= 1,
 	BOARD_TYPE_DVP_EVB_18XX	= 2,
+
+	NUM_BOARD_TYPES,
+};
+
+/* board type values used by the firmware in the SCR_PAD2 register */
+enum {
+	SCR_PAD2_BOARD_TYPE_FPGA	= 0xB1,
+	SCR_PAD2_BOARD_TYPE_HDK		= 0xB2,
+	SCR_PAD2_BOARD_TYPE_DVP_EVB	= 0xB3,
 };
 
 struct wl18xx_mac_and_phy_params {