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yaml
---
r: 221671
b: refs/heads/master
c: d0013c9
h: refs/heads/master
i:
  221669: d199fbe
  221667: 341c6fd
  221663: 3294a30
v: v3
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Guennadi Liakhovetski authored and Paul Mundt committed Nov 8, 2010
1 parent 6d30f6f commit 8b07af5
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Showing 2 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 6af26c6c99f01e810f9944543df810e320284aa3
refs/heads/master: d0013c9e3bc75b3e1652bd5999a9a8d56a822ce4
6 changes: 3 additions & 3 deletions trunk/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ static struct clk r_clk = {
* Default rate for the root input clock, reset this with clk_set_rate()
* from the platform code.
*/
struct clk extal_clk = {
static struct clk extal_clk = {
.rate = 33333333,
};

Expand Down Expand Up @@ -111,7 +111,7 @@ static struct clk div3_clk = {
.parent = &pll_clk,
};

struct clk *main_clks[] = {
static struct clk *main_clks[] = {
&r_clk,
&extal_clk,
&fll_clk,
Expand Down Expand Up @@ -156,7 +156,7 @@ struct clk div4_clks[DIV4_NR] = {

enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };

struct clk div6_clks[DIV6_NR] = {
static struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
[DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
[DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
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