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yaml --- r: 313267 b: refs/heads/master c: 5fc0b42 h: refs/heads/master i: 313265: f392c5c 313263: 7a4d41e v: v3
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AnilKumar Ch
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Tony Lindgren
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Jul 3, 2012
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| refs/heads/master: c7d0effa49e05df0881469a72cb381ac5e009e92 | ||
| refs/heads/master: 5fc0b42a98556bd9f01cecc6a64fcbd15ec363f0 |
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| /* | ||
| * Device Tree Source for AM33XX SoC | ||
| * | ||
| * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| * | ||
| * This file is licensed under the terms of the GNU General Public License | ||
| * version 2. This program is licensed "as is" without any warranty of any | ||
| * kind, whether express or implied. | ||
| */ | ||
|
|
||
| /include/ "skeleton.dtsi" | ||
|
|
||
| / { | ||
| compatible = "ti,am33xx"; | ||
|
|
||
| aliases { | ||
| serial0 = &uart1; | ||
| serial1 = &uart2; | ||
| serial2 = &uart3; | ||
| serial3 = &uart4; | ||
| serial4 = &uart5; | ||
| serial5 = &uart6; | ||
| }; | ||
|
|
||
| cpus { | ||
| cpu@0 { | ||
| compatible = "arm,cortex-a8"; | ||
| }; | ||
| }; | ||
|
|
||
| /* | ||
| * The soc node represents the soc top level view. It is uses for IPs | ||
| * that are not memory mapped in the MPU view or for the MPU itself. | ||
| */ | ||
| soc { | ||
| compatible = "ti,omap-infra"; | ||
| mpu { | ||
| compatible = "ti,omap3-mpu"; | ||
| ti,hwmods = "mpu"; | ||
| }; | ||
| }; | ||
|
|
||
| /* | ||
| * XXX: Use a flat representation of the AM33XX interconnect. | ||
| * The real AM33XX interconnect network is quite complex.Since | ||
| * that will not bring real advantage to represent that in DT | ||
| * for the moment, just use a fake OCP bus entry to represent | ||
| * the whole bus hierarchy. | ||
| */ | ||
| ocp { | ||
| compatible = "simple-bus"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| ranges; | ||
| ti,hwmods = "l3_main"; | ||
|
|
||
| intc: interrupt-controller@48200000 { | ||
| compatible = "ti,omap2-intc"; | ||
| interrupt-controller; | ||
| #interrupt-cells = <1>; | ||
| ti,intc-size = <128>; | ||
| reg = <0x48200000 0x1000>; | ||
| }; | ||
|
|
||
| gpio1: gpio@44e07000 { | ||
| compatible = "ti,omap4-gpio"; | ||
| ti,hwmods = "gpio1"; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <1>; | ||
| }; | ||
|
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||
| gpio2: gpio@4804C000 { | ||
| compatible = "ti,omap4-gpio"; | ||
| ti,hwmods = "gpio2"; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <1>; | ||
| }; | ||
|
|
||
| gpio3: gpio@481AC000 { | ||
| compatible = "ti,omap4-gpio"; | ||
| ti,hwmods = "gpio3"; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <1>; | ||
| }; | ||
|
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||
| gpio4: gpio@481AE000 { | ||
| compatible = "ti,omap4-gpio"; | ||
| ti,hwmods = "gpio4"; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <1>; | ||
| }; | ||
|
|
||
| uart1: serial@44E09000 { | ||
| compatible = "ti,omap3-uart"; | ||
| ti,hwmods = "uart1"; | ||
| clock-frequency = <48000000>; | ||
| }; | ||
|
|
||
| uart2: serial@48022000 { | ||
| compatible = "ti,omap3-uart"; | ||
| ti,hwmods = "uart2"; | ||
| clock-frequency = <48000000>; | ||
| }; | ||
|
|
||
| uart3: serial@48024000 { | ||
| compatible = "ti,omap3-uart"; | ||
| ti,hwmods = "uart3"; | ||
| clock-frequency = <48000000>; | ||
| }; | ||
|
|
||
| uart4: serial@481A6000 { | ||
| compatible = "ti,omap3-uart"; | ||
| ti,hwmods = "uart4"; | ||
| clock-frequency = <48000000>; | ||
| }; | ||
|
|
||
| uart5: serial@481A8000 { | ||
| compatible = "ti,omap3-uart"; | ||
| ti,hwmods = "uart5"; | ||
| clock-frequency = <48000000>; | ||
| }; | ||
|
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||
| uart6: serial@481AA000 { | ||
| compatible = "ti,omap3-uart"; | ||
| ti,hwmods = "uart6"; | ||
| clock-frequency = <48000000>; | ||
| }; | ||
|
|
||
| i2c1: i2c@44E0B000 { | ||
| compatible = "ti,omap4-i2c"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| ti,hwmods = "i2c1"; | ||
| }; | ||
|
|
||
| i2c2: i2c@4802A000 { | ||
| compatible = "ti,omap4-i2c"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| ti,hwmods = "i2c2"; | ||
| }; | ||
|
|
||
| i2c3: i2c@4819C000 { | ||
| compatible = "ti,omap4-i2c"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| ti,hwmods = "i2c3"; | ||
| }; | ||
|
|
||
| mcspi1: spi@48030000 { | ||
| compatible = "ti,omap2-mcspi"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| ti,hwmods = "spi0"; | ||
| ti,spi-num-cs = <4>; | ||
| }; | ||
|
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||
| mcspi2: spi@481Aa000 { | ||
| compatible = "ti,omap2-mcspi"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| ti,hwmods = "spi1"; | ||
| ti,spi-num-cs = <2>; | ||
| }; | ||
|
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||
| mmc1: mmc@48060000 { | ||
| compatible = "ti,omap3-hsmmc"; | ||
| ti,hwmods = "mmc1"; | ||
| }; | ||
|
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||
| mmc2: mmc@481D8000 { | ||
| compatible = "ti,omap3-hsmmc"; | ||
| ti,hwmods = "mmc2"; | ||
| }; | ||
|
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||
| mmc3: mmc@47810000 { | ||
| compatible = "ti,omap3-hsmmc"; | ||
| ti,hwmods = "mmc3"; | ||
| }; | ||
| }; | ||
| }; |