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Merge tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel…
…/git/broonie/regmap Pull regmap updates from Mark Brown: "A small but useful set of regmap updates this time around: - An abstraction for bitfields within a register map contributed by Srinivas Kandagatla, allowing drivers to cope more easily when hardware designers randomly move things about (mainly when talking to things like system controllers). - Changes from Lars-Peter Clausen to allow the MMIO regmap to be used from hard IRQ context. - Small improvements to the cache infrastructure and performance, including a default cache sync operation so now all regmaps can sync easily. There's also a pinctrl driver making use of the new bitfield API, merged here for dependency reasons. There will be a simple add/add conflict with the pinctrl tree as a result." * tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap: pinctrl: st: Remove unnecessary use of of_match_ptr macro pinctrl: st: fix return value check pinctrl: st: Add pinctrl and pinconf support. regmap: debugfs: Suppress cache for partial register files regmap: Add regmap_field APIs regmap: core: Cache all registers by default when cache is enabled regmap: Implemented default cache sync operation regmap: Make regmap-mmio usable from atomic contexts regmap: regcache: Fixup locking for custom lock callbacks regmap: debugfs: Fix return from regmap_debugfs_get_dump_start regmap: debugfs: Don't mark lockdep as broken due to debugfs write regmap: rbtree: Use range information to allocate nodes regmap: rbtree: Factor out node allocation regmap: Make regmap_check_range_table() a public API regmap: Add support for discarding parts of the register cache
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Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
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*ST pin controller. | ||
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Each multi-function pin is controlled, driven and routed through the | ||
PIO multiplexing block. Each pin supports GPIO functionality (ALT0) | ||
and multiple alternate functions(ALT1 - ALTx) that directly connect | ||
the pin to different hardware blocks. | ||
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When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and | ||
Pull Up (PU) are driven by the related PIO block. | ||
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ST pinctrl driver controls PIO multiplexing block and also interacts with | ||
gpio driver to configure a pin. | ||
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Required properties: (PIO multiplexing block) | ||
- compatible : should be "st,<SOC>-<pio-block>-pinctrl" | ||
like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on. | ||
- gpio-controller : Indicates this device is a GPIO controller | ||
- #gpio-cells : Should be one. The first cell is the pin number. | ||
- st,retime-pin-mask : Should be mask to specify which pins can be retimed. | ||
If the property is not present, it is assumed that all the pins in the | ||
bank are capable of retiming. Retiming is mainly used to improve the | ||
IO timing margins of external synchronous interfaces. | ||
- st,bank-name : Should be a name string for this bank as | ||
specified in datasheet. | ||
- st,syscfg : Should be a phandle of the syscfg node. | ||
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Example: | ||
pin-controller-sbc { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
compatible = "st,stih415-sbc-pinctrl"; | ||
st,syscfg = <&syscfg_sbc>; | ||
ranges = <0 0xfe610000 0x5000>; | ||
PIO0: gpio@fe610000 { | ||
gpio-controller; | ||
#gpio-cells = <1>; | ||
reg = <0 0x100>; | ||
st,bank-name = "PIO0"; | ||
}; | ||
... | ||
pin-functions nodes follow... | ||
}; | ||
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Contents of function subnode node: | ||
---------------------- | ||
Required properties for pin configuration node: | ||
- st,pins : Child node with list of pins with configuration. | ||
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Below is the format of how each pin conf should look like. | ||
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<bank offset mux mode rt_type rt_delay rt_clk> | ||
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Every PIO is represented with 4-7 parameters depending on retime configuration. | ||
Each parameter is explained as below. | ||
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-bank : Should be bank phandle to which this PIO belongs. | ||
-offset : Offset in the PIO bank. | ||
-mux : Should be alternate function number associated this pin. | ||
Use same numbers from datasheet. | ||
-mode :pin configuration is selected from one of the below values. | ||
IN | ||
IN_PU | ||
OUT | ||
BIDIR | ||
BIDIR_PU | ||
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-rt_type Retiming Configuration for the pin. | ||
Possible retime configuration are: | ||
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------- ------------- | ||
value args | ||
------- ------------- | ||
NICLK <delay> <clk> | ||
ICLK_IO <delay> <clk> | ||
BYPASS <delay> | ||
DE_IO <delay> <clk> | ||
SE_ICLK_IO <delay> <clk> | ||
SE_NICLK_IO <delay> <clk> | ||
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- delay is retime delay in pico seconds as mentioned in data sheet. | ||
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- rt_clk :clk to be use for retime. | ||
Possible values are: | ||
CLK_A | ||
CLK_B | ||
CLK_C | ||
CLK_D | ||
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Example of mmcclk pin which is a bi-direction pull pu with retime config | ||
as non inverted clock retimed with CLK_B and delay of 0 pico seconds: | ||
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pin-controller { | ||
... | ||
mmc0 { | ||
pinctrl_mmc: mmc { | ||
st,pins { | ||
mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; | ||
... | ||
}; | ||
}; | ||
... | ||
}; | ||
}; | ||
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sdhci0:sdhci@fe810000{ | ||
... | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&pinctrl_mmc>; | ||
}; |
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