---

yaml
---
r: 58839
b: refs/heads/master
c: 29440a2
h: refs/heads/master
i:
  58837: bcb11d1
  58835: d0b4a38
  58831: 0c0854b
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 474f1a667d4bd40b6dcacc6870b70f4d2ba4e155
+refs/heads/master: 29440a2b4cd37e32dfe0fa60ef1665775b24dab1

trunk/arch/blackfin/kernel/Makefile

@@ -7,7 +7,7 @@ extra-y := init_task.o vmlinux.lds
 obj-y := \
 	entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
 	sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \
-	fixed_code.o
+	fixed_code.o cplbinit.o cacheinit.o
 
 obj-$(CONFIG_BF53x)		     += bfin_gpio.o
 obj-$(CONFIG_BF561)		     += bfin_gpio.o

trunk/arch/blackfin/kernel/cacheinit.c

@@ -0,0 +1,66 @@
+/*
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/cpu.h>
+
+#include <asm/cacheflush.h>
+#include <asm/blackfin.h>
+#include <asm/cplbinit.h>
+
+#if defined(CONFIG_BLKFIN_CACHE)
+void bfin_icache_init(void)
+{
+	unsigned long *table = icplb_table;
+	unsigned long ctrl;
+	int i;
+
+	for (i = 0; i < MAX_CPLBS; i++) {
+		unsigned long addr = *table++;
+		unsigned long data = *table++;
+		if (addr == (unsigned long)-1)
+			break;
+		bfin_write32(ICPLB_ADDR0 + i * 4, addr);
+		bfin_write32(ICPLB_DATA0 + i * 4, data);
+	}
+	ctrl = bfin_read_IMEM_CONTROL();
+	ctrl |= IMC | ENICPLB;
+	bfin_write_IMEM_CONTROL(ctrl);
+}
+#endif
+
+#if defined(CONFIG_BLKFIN_DCACHE)
+void bfin_dcache_init(void)
+{
+	unsigned long *table = dcplb_table;
+	unsigned long ctrl;
+	int i;
+
+	for (i = 0; i < MAX_CPLBS; i++) {
+		unsigned long addr = *table++;
+		unsigned long data = *table++;
+		if (addr == (unsigned long)-1)
+			break;
+		bfin_write32(DCPLB_ADDR0 + i * 4, addr);
+		bfin_write32(DCPLB_DATA0 + i * 4, data);
+	}
+	ctrl = bfin_read_DMEM_CONTROL();
+	ctrl |= DMEM_CNTR;
+	bfin_write_DMEM_CONTROL(ctrl);
+}
+#endif