---

yaml
---
r: 325542
b: refs/heads/master
c: dc59817
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 7f98961c0d4bdebc4508c59cead7f349e47feb7f
+refs/heads/master: dc598176bbd7dfbcfcd6177d14b10768c59effae

trunk/drivers/staging/comedi/drivers/s626.c

@@ -99,7 +99,6 @@ struct s626_private {
 	uint16_t Dacpol;	/* Image of DAC polarity register. */
 	uint8_t TrimSetpoint[12];	/* Images of TrimDAC setpoints */
 	/* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
-	uint16_t WDInterval;	/* Image of MISC2 watchdog interval control bits. */
 	uint32_t I2CAdrs;
 	/* I2C device address for onboard EEPROM (board rev dependent). */
 	/*   short         I2Cards; */
@@ -2666,12 +2665,6 @@ static void s626_initialize(struct comedi_device *dev)
 	for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
 		SetDAC(dev, chan, 0);
 
-	/* Init image of watchdog timer interval in WRMISC2.  This image
-	 * maintains the value of the control bits of MISC2 are
-	 * continuously reset to zero as long as the WD timer is disabled.
-	 */
-	devpriv->WDInterval = 0;
-
 	/* Init Counter Interrupt enab mask for RDMISC2.  This mask is
 	 * applied against MISC2 when testing to determine which timer
 	 * events are requesting interrupt service.