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arm64: dts: imx8: switch to two cell scu clock binding
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switch to two cell scu clock binding

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Dong Aisheng authored and Shawn Guo committed Mar 29, 2021
1 parent e783b6b commit 26de33a
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Showing 6 changed files with 68 additions and 52 deletions.
24 changes: 12 additions & 12 deletions arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,7 @@ adma_subsys: bus@59000000 {
uart0_lpcg: clock-controller@5a460000 {
reg = <0x5a460000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_UART0_CLK>,
clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart0_lpcg_baud_clk",
Expand All @@ -124,7 +124,7 @@ adma_subsys: bus@59000000 {
uart1_lpcg: clock-controller@5a470000 {
reg = <0x5a470000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_UART1_CLK>,
clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart1_lpcg_baud_clk",
Expand All @@ -135,7 +135,7 @@ adma_subsys: bus@59000000 {
uart2_lpcg: clock-controller@5a480000 {
reg = <0x5a480000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_UART2_CLK>,
clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart2_lpcg_baud_clk",
Expand All @@ -146,7 +146,7 @@ adma_subsys: bus@59000000 {
uart3_lpcg: clock-controller@5a490000 {
reg = <0x5a490000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_UART3_CLK>,
clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart3_lpcg_baud_clk",
Expand All @@ -159,7 +159,7 @@ adma_subsys: bus@59000000 {
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_0>;
status = "disabled";
Expand All @@ -170,7 +170,7 @@ adma_subsys: bus@59000000 {
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_1>;
status = "disabled";
Expand All @@ -181,7 +181,7 @@ adma_subsys: bus@59000000 {
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_2>;
status = "disabled";
Expand All @@ -192,7 +192,7 @@ adma_subsys: bus@59000000 {
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
clock-names = "per";
assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_I2C_3>;
status = "disabled";
Expand All @@ -201,7 +201,7 @@ adma_subsys: bus@59000000 {
i2c0_lpcg: clock-controller@5ac00000 {
reg = <0x5ac00000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_I2C0_CLK>,
clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c0_lpcg_clk",
Expand All @@ -212,7 +212,7 @@ adma_subsys: bus@59000000 {
i2c1_lpcg: clock-controller@5ac10000 {
reg = <0x5ac10000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_I2C1_CLK>,
clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c1_lpcg_clk",
Expand All @@ -223,7 +223,7 @@ adma_subsys: bus@59000000 {
i2c2_lpcg: clock-controller@5ac20000 {
reg = <0x5ac20000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_I2C2_CLK>,
clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c2_lpcg_clk",
Expand All @@ -234,7 +234,7 @@ adma_subsys: bus@59000000 {
i2c3_lpcg: clock-controller@5ac30000 {
reg = <0x5ac30000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_ADMA_I2C3_CLK>,
clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "i2c3_lpcg_clk",
Expand Down
14 changes: 7 additions & 7 deletions arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -112,7 +112,7 @@ conn_subsys: bus@5b000000 {
sdhc0_lpcg: clock-controller@5b200000 {
reg = <0x5b200000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_SDHC0_CLK>,
clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
Expand All @@ -125,7 +125,7 @@ conn_subsys: bus@5b000000 {
sdhc1_lpcg: clock-controller@5b210000 {
reg = <0x5b210000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_SDHC1_CLK>,
clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
Expand All @@ -138,7 +138,7 @@ conn_subsys: bus@5b000000 {
sdhc2_lpcg: clock-controller@5b220000 {
reg = <0x5b220000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_SDHC2_CLK>,
clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>, <&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
Expand All @@ -151,8 +151,8 @@ conn_subsys: bus@5b000000 {
enet0_lpcg: clock-controller@5b230000 {
reg = <0x5b230000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
<&clk IMX_CONN_ENET0_ROOT_CLK>,
clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
Expand All @@ -168,8 +168,8 @@ conn_subsys: bus@5b000000 {
enet1_lpcg: clock-controller@5b240000 {
reg = <0x5b240000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
<&clk IMX_CONN_ENET1_ROOT_CLK>,
clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
Expand Down
64 changes: 40 additions & 24 deletions arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -157,9 +157,11 @@ lsio_subsys: bus@5d000000 {
pwm0_lpcg: clock-controller@5d400000 {
reg = <0x5d400000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM0_CLK>, <&clk IMX_LSIO_PWM0_CLK>,
<&clk IMX_LSIO_PWM0_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM0_CLK>;
clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
Expand All @@ -174,9 +176,11 @@ lsio_subsys: bus@5d000000 {
pwm1_lpcg: clock-controller@5d410000 {
reg = <0x5d410000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM1_CLK>, <&clk IMX_LSIO_PWM1_CLK>,
<&clk IMX_LSIO_PWM1_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM1_CLK>;
clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
Expand All @@ -191,9 +195,11 @@ lsio_subsys: bus@5d000000 {
pwm2_lpcg: clock-controller@5d420000 {
reg = <0x5d420000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM2_CLK>, <&clk IMX_LSIO_PWM2_CLK>,
<&clk IMX_LSIO_PWM2_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM2_CLK>;
clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
Expand All @@ -208,9 +214,11 @@ lsio_subsys: bus@5d000000 {
pwm3_lpcg: clock-controller@5d430000 {
reg = <0x5d430000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM3_CLK>, <&clk IMX_LSIO_PWM3_CLK>,
<&clk IMX_LSIO_PWM3_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM3_CLK>;
clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
Expand All @@ -225,9 +233,11 @@ lsio_subsys: bus@5d000000 {
pwm4_lpcg: clock-controller@5d440000 {
reg = <0x5d440000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM4_CLK>, <&clk IMX_LSIO_PWM4_CLK>,
<&clk IMX_LSIO_PWM4_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM4_CLK>;
clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
Expand All @@ -242,9 +252,11 @@ lsio_subsys: bus@5d000000 {
pwm5_lpcg: clock-controller@5d450000 {
reg = <0x5d450000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM5_CLK>, <&clk IMX_LSIO_PWM5_CLK>,
<&clk IMX_LSIO_PWM5_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM5_CLK>;
clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
Expand All @@ -259,9 +271,11 @@ lsio_subsys: bus@5d000000 {
pwm6_lpcg: clock-controller@5d460000 {
reg = <0x5d460000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM6_CLK>, <&clk IMX_LSIO_PWM6_CLK>,
<&clk IMX_LSIO_PWM6_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM6_CLK>;
clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
Expand All @@ -276,9 +290,11 @@ lsio_subsys: bus@5d000000 {
pwm7_lpcg: clock-controller@5d470000 {
reg = <0x5d470000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_LSIO_PWM7_CLK>, <&clk IMX_LSIO_PWM7_CLK>,
<&clk IMX_LSIO_PWM7_CLK>, <&lsio_bus_clk>,
<&clk IMX_LSIO_PWM7_CLK>;
clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>,
<&lsio_bus_clk>,
<&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
<IMX_LPCG_CLK_6>;
Expand Down
4 changes: 2 additions & 2 deletions arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -133,7 +133,7 @@
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
Expand All @@ -151,7 +151,7 @@

/* SD */
&usdhc2 {
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
Expand Down
4 changes: 2 additions & 2 deletions arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -173,7 +173,7 @@
};

&usdhc1 {
assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
Expand All @@ -185,7 +185,7 @@
};

&usdhc2 {
assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
Expand Down
10 changes: 5 additions & 5 deletions arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
Expand All @@ -69,7 +69,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
Expand All @@ -80,7 +80,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
Expand All @@ -91,7 +91,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_A35_CLK>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
#cooling-cells = <2>;
};
Expand Down Expand Up @@ -165,7 +165,7 @@

clk: clock-controller {
compatible = "fsl,imx8qxp-clk";
#clock-cells = <1>;
#clock-cells = <2>;
clocks = <&xtal32k &xtal24m>;
clock-names = "xtal_32KHz", "xtal_24Mhz";
};
Expand Down

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