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Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' a…
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…nd 'clk-imx' into clk-next

 - Qualcomm QCS404 CDSP clk support
 - Qualcomm QCS404 Turing clk support
 - Mediatek MT8183 clock support
 - Mediatek MT8516 clock support
 - Milbeaut M10V clk controller support

* clk-renesas:
  clk: renesas: rcar-gen3: Remove unused variable
  clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value
  clk: renesas: r8a77980: Fix RPC-IF module clock's parent
  clk: renesas: rcar-gen3: Rename DRIF clocks
  clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
  clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
  clk: renesas: rcar-gen3: Correct parent clock of HS-USB
  clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
  clk: renesas: r8a774c0: Add Z2 clock
  clk: renesas: r8a77990: Add Z2 clock
  clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents
  math64: New DIV64_U64_ROUND_CLOSEST helper
  clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
  clk: renesas: r9a06g032: Add missing PCI USB clock
  clk: renesas: r7s9210: Always use readl()
  clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()

* clk-qcom:
  clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998
  clk: qcom: Add QCS404 TuringCC
  clk: qcom: branch: Add AON clock ops
  dt-bindings: clock: Introduce Qualcomm Turing Clock controller
  clk: qcom: gcc-qcs404: Add CDSP related clocks and resets

* clk-mtk:
  clk: mediatek: add clock driver for MT8516
  dt-bindings: mediatek: apmixedsys: add support for MT8516
  dt-bindings: mediatek: infracfg: add support for MT8516
  dt-bindings: mediatek: topckgen: add support for MT8516
  clk: mediatek: Allow changing PLL rate when it is off
  clk: mediatek: Add MT8183 clock support
  clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
  clk: mediatek: Add dt-bindings for MT8183 clocks
  dt-bindings: ARM: Mediatek: Document bindings for MT8183
  clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
  clk: mediatek: Add new clkmux register API
  clk: mediatek: Disable tuner_en before change PLL rate

* clk-milbeaut:
  clock: milbeaut: Add Milbeaut M10V clock controller
  dt-bindings: clock: milbeaut: add Milbeaut clock description

* clk-imx:
  clk: imx: correct pfdv2 gate_bit/vld_bit operations
  clk: imx: clk-pllv3: mark expected switch fall-throughs
  clk: imx8mq: Add dsi_ipg_div
  clk: imx: pllv4: add fractional-N pll support
  clk: imx: keep uart clock on during system boot
  clk: imx: correct i.MX7D AV PLL num/denom offset
  clk: imx6sll: Fix mispelling uart4_serial as serail
  clk: imx: pll14xx: drop unused variable
  clk: imx: rename clk-imx51-imx53.c to clk-imx5.c
  clk: imx5: Fix i.MX50 ESDHC clock registers
  clk: imx5: Fix i.MX50 mainbus clock registers
  clk: imx: Remove unused imx_get_clk_hw_fixed
  dt-bindings: clock: imx7ulp: remove SNVS clock
  clk: imx7ulp: remove snvs clock
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Stephen Boyd committed May 7, 2019
6 parents e93c9c9 + c2f0705 + c0ee0e4 + db077fe + 6a6ba5b + a5a627c commit 2ed3b91
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Showing 72 changed files with 5,451 additions and 204 deletions.
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Expand Up @@ -14,6 +14,8 @@ Required Properties:
- "mediatek,mt7629-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
- "mediatek,mt8183-apmixedsys", "syscon"
- "mediatek,mt8516-apmixedsys"
- #clock-cells: Must be 1

The apmixedsys controller uses the common clk binding from
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Expand Up @@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt8183-audiosys", "syscon"
- #clock-cells: Must be 1

The AUDSYS controller uses the common clk binding from
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22 changes: 22 additions & 0 deletions Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
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MediaTek CAMSYS controller
============================

The MediaTek camsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
- "mediatek,mt8183-camsys", "syscon"
- #clock-cells: Must be 1

The camsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

camsys: camsys@1a000000 {
compatible = "mediatek,mt8183-camsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
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Expand Up @@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6797-imgsys", "syscon"
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
- "mediatek,mt8183-imgsys", "syscon"
- #clock-cells: Must be 1

The imgsys controller uses the common clk binding from
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Expand Up @@ -15,6 +15,8 @@ Required Properties:
- "mediatek,mt7629-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- "mediatek,mt8183-infracfg", "syscon"
- "mediatek,mt8516-infracfg", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1

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43 changes: 43 additions & 0 deletions Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt
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Mediatek IPU controller
============================

The Mediatek ipu controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
- "mediatek,mt8183-ipu_conn", "syscon"
- "mediatek,mt8183-ipu_adl", "syscon"
- "mediatek,mt8183-ipu_core0", "syscon"
- "mediatek,mt8183-ipu_core1", "syscon"
- #clock-cells: Must be 1

The ipu controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

ipu_conn: syscon@19000000 {
compatible = "mediatek,mt8183-ipu_conn", "syscon";
reg = <0 0x19000000 0 0x1000>;
#clock-cells = <1>;
};

ipu_adl: syscon@19010000 {
compatible = "mediatek,mt8183-ipu_adl", "syscon";
reg = <0 0x19010000 0 0x1000>;
#clock-cells = <1>;
};

ipu_core0: syscon@19180000 {
compatible = "mediatek,mt8183-ipu_core0", "syscon";
reg = <0 0x19180000 0 0x1000>;
#clock-cells = <1>;
};

ipu_core1: syscon@19280000 {
compatible = "mediatek,mt8183-ipu_core1", "syscon";
reg = <0 0x19280000 0 0x1000>;
#clock-cells = <1>;
};
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ Required Properties:

- compatible: Should be one of:
- "mediatek,mt2712-mcucfg", "syscon"
- "mediatek,mt8183-mcucfg", "syscon"
- #clock-cells: Must be 1

The mcucfg controller uses the common clk binding from
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Expand Up @@ -7,6 +7,7 @@ Required Properties:

- compatible: Should be one of:
- "mediatek,mt2712-mfgcfg", "syscon"
- "mediatek,mt8183-mfgcfg", "syscon"
- #clock-cells: Must be 1

The mfgcfg controller uses the common clk binding from
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Expand Up @@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6797-mmsys", "syscon"
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- "mediatek,mt8183-mmsys", "syscon"
- #clock-cells: Must be 1

The mmsys controller uses the common clk binding from
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Expand Up @@ -14,6 +14,8 @@ Required Properties:
- "mediatek,mt7629-topckgen"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8173-topckgen"
- "mediatek,mt8183-topckgen", "syscon"
- "mediatek,mt8516-topckgen"
- #clock-cells: Must be 1

The topckgen controller uses the common clk binding from
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Expand Up @@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6797-vdecsys", "syscon"
- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
- "mediatek,mt8183-vdecsys", "syscon"
- #clock-cells: Must be 1

The vdecsys controller uses the common clk binding from
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Expand Up @@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2712-vencsys", "syscon"
- "mediatek,mt6797-vencsys", "syscon"
- "mediatek,mt8173-vencsys", "syscon"
- "mediatek,mt8183-vencsys", "syscon"
- #clock-cells: Must be 1

The vencsys controller uses the common clk binding from
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73 changes: 73 additions & 0 deletions Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/clock/milbeaut-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Milbeaut SoCs Clock Controller Binding

maintainers:
- Taichi Sugaya <sugaya.taichi@socionext.com>

description: |
Milbeaut SoCs Clock controller is an integrated clock controller, which
generates and supplies to all modules.
This binding uses common clock bindings
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
properties:
compatible:
oneOf:
- items:
- enum:
- socionext,milbeaut-m10v-ccu
clocks:
maxItems: 1
description: external clock

'#clock-cells':
const: 1

required:
- compatible
- reg
- clocks
- '#clock-cells'

examples:
# Clock controller node:
- |
m10v-clk-ctrl@1d021000 {
compatible = "socionext,milbeaut-m10v-clk-ccu";
reg = <0x1d021000 0x4000>;
#clock-cells = <1>;
clocks = <&clki40mhz>;
};
# Required an external clock for Clock controller node:
- |
clocks {
clki40mhz: clki40mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
/* other clocks */
};
# The clock consumer shall specify the desired clock-output of the clock
# controller as below by specifying output-id in its "clk" phandle cell.
# 2: uart
# 4: 32-bit timer
# 7: UHS-I/II
- |
serial@1e700010 {
compatible = "socionext,milbeaut-usio-uart";
reg = <0x1e700010 0x10>;
interrupts = <0 141 0x4>, <0 149 0x4>;
interrupt-names = "rx", "tx";
clocks = <&clk 2>;
};
...
19 changes: 19 additions & 0 deletions Documentation/devicetree/bindings/clock/qcom,turingcc.txt
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@@ -0,0 +1,19 @@
Qualcomm Turing Clock & Reset Controller Binding
------------------------------------------------

Required properties :
- compatible: shall contain "qcom,qcs404-turingcc".
- reg: shall contain base register location and length.
- clocks: ahb clock for the TuringCC
- #clock-cells: from common clock binding, shall contain 1.
- #reset-cells: from common reset binding, shall contain 1.

Example:
turingcc: clock-controller@800000 {
compatible = "qcom,qcs404-turingcc";
reg = <0x00800000 0x30000>;
clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;

#clock-cells = <1>;
#reset-cells = <1>;
};
1 change: 1 addition & 0 deletions drivers/clk/Makefile
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Expand Up @@ -34,6 +34,7 @@ obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
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