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ASoC: fsl_spdif: Add new registers included on i.MX8ULP
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There are some new registers added on i.MX8ULP, they are
the SPDIF transmit Professional C channel registers,
192bit SPDIF receive C channel registers, and 192bit SPDIF
transmit C channel registers.

There are two output lines, SPDIF_OUT1 and SPDIF_OUT2, the
original REG_SPDIF_STCSCH and REG_SPDIF_STCSCL are used for
SPDIF_OUT1, the new REG_SPDIF_STCSPH and REG_SPDIF_STCSPL
are used for SPDIF_OUT2, the 192bit SPDIF C channel registers
are used for both.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1647408538-2982-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Shengjiu Wang authored and Mark Brown committed Mar 17, 2022
1 parent b26f965 commit 638cec3
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Showing 2 changed files with 65 additions and 1 deletion.
52 changes: 51 additions & 1 deletion sound/soc/fsl/fsl_spdif.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,7 @@ static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
* @shared_root_clock: flag of sharing a clock source with others;
* so the driver shouldn't set root clock rate
* @raw_capture_mode: if raw capture mode support
* @cchannel_192b: if there are registers for 192bits C channel data
* @interrupts: interrupt number
* @tx_burst: tx maxburst size
* @rx_burst: rx maxburst size
Expand All @@ -59,6 +60,7 @@ struct fsl_spdif_soc_data {
bool imx;
bool shared_root_clock;
bool raw_capture_mode;
bool cchannel_192b;
u32 interrupts;
u32 tx_burst;
u32 rx_burst;
Expand Down Expand Up @@ -196,6 +198,7 @@ static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {
.tx_burst = 2, /* Applied for EDMA */
.rx_burst = 2, /* Applied for EDMA */
.tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
.cchannel_192b = true,
};

/* Check if clk is a root clock that does not share clock source with others */
Expand Down Expand Up @@ -441,6 +444,23 @@ static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);

dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);

if (spdif_priv->soc->cchannel_192b) {
ch_status = (bitrev8(ctrl->ch_status[0]) << 24) |
(bitrev8(ctrl->ch_status[1]) << 16) |
(bitrev8(ctrl->ch_status[2]) << 8) |
bitrev8(ctrl->ch_status[3]);

regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000);

/*
* The first 32bit should be in REG_SPDIF_STCCA_31_0 register,
* but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP
* then can get correct result with HDMI analyzer capture.
* There is a hardware bug here.
*/
regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status);
}
}

/* Set SPDIF PhaseConfig register for rx clock */
Expand Down Expand Up @@ -1229,6 +1249,8 @@ static const struct reg_default fsl_spdif_reg_defaults[] = {
{REG_SPDIF_STR, 0x00000000},
{REG_SPDIF_STCSCH, 0x00000000},
{REG_SPDIF_STCSCL, 0x00000000},
{REG_SPDIF_STCSPH, 0x00000000},
{REG_SPDIF_STCSPL, 0x00000000},
{REG_SPDIF_STC, 0x00020f00},
};

Expand All @@ -1248,8 +1270,22 @@ static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
case REG_SPDIF_SRQ:
case REG_SPDIF_STCSCH:
case REG_SPDIF_STCSCL:
case REG_SPDIF_STCSPH:
case REG_SPDIF_STCSPL:
case REG_SPDIF_SRFM:
case REG_SPDIF_STC:
case REG_SPDIF_SRCCA_31_0:
case REG_SPDIF_SRCCA_63_32:
case REG_SPDIF_SRCCA_95_64:
case REG_SPDIF_SRCCA_127_96:
case REG_SPDIF_SRCCA_159_128:
case REG_SPDIF_SRCCA_191_160:
case REG_SPDIF_STCCA_31_0:
case REG_SPDIF_STCCA_63_32:
case REG_SPDIF_STCCA_95_64:
case REG_SPDIF_STCCA_127_96:
case REG_SPDIF_STCCA_159_128:
case REG_SPDIF_STCCA_191_160:
return true;
default:
return false;
Expand All @@ -1268,6 +1304,12 @@ static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
case REG_SPDIF_SRU:
case REG_SPDIF_SRQ:
case REG_SPDIF_SRFM:
case REG_SPDIF_SRCCA_31_0:
case REG_SPDIF_SRCCA_63_32:
case REG_SPDIF_SRCCA_95_64:
case REG_SPDIF_SRCCA_127_96:
case REG_SPDIF_SRCCA_159_128:
case REG_SPDIF_SRCCA_191_160:
return true;
default:
return false;
Expand All @@ -1286,7 +1328,15 @@ static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
case REG_SPDIF_STR:
case REG_SPDIF_STCSCH:
case REG_SPDIF_STCSCL:
case REG_SPDIF_STCSPH:
case REG_SPDIF_STCSPL:
case REG_SPDIF_STC:
case REG_SPDIF_STCCA_31_0:
case REG_SPDIF_STCCA_63_32:
case REG_SPDIF_STCCA_95_64:
case REG_SPDIF_STCCA_127_96:
case REG_SPDIF_STCCA_159_128:
case REG_SPDIF_STCCA_191_160:
return true;
default:
return false;
Expand All @@ -1298,7 +1348,7 @@ static const struct regmap_config fsl_spdif_regmap_config = {
.reg_stride = 4,
.val_bits = 32,

.max_register = REG_SPDIF_STC,
.max_register = REG_SPDIF_STCCA_191_160,
.reg_defaults = fsl_spdif_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
.readable_reg = fsl_spdif_readable_reg,
Expand Down
14 changes: 14 additions & 0 deletions sound/soc/fsl/fsl_spdif.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,9 +31,23 @@
#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
#define REG_SPDIF_STCSPH 0x3C /* SPDIFTxCChannel_Prof_h Register */
#define REG_SPDIF_STCSPL 0x40 /* SPDIFTxCChannel_Prof_l Register */
#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */

#define REG_SPDIF_SRCCA_31_0 0x60 /* SPDIF receive C channel register, bits 31-0 */
#define REG_SPDIF_SRCCA_63_32 0x64 /* SPDIF receive C channel register, bits 63-32 */
#define REG_SPDIF_SRCCA_95_64 0x68 /* SPDIF receive C channel register, bits 95-64 */
#define REG_SPDIF_SRCCA_127_96 0x6C /* SPDIF receive C channel register, bits 127-96 */
#define REG_SPDIF_SRCCA_159_128 0x70 /* SPDIF receive C channel register, bits 159-128 */
#define REG_SPDIF_SRCCA_191_160 0x74 /* SPDIF receive C channel register, bits 191-160 */
#define REG_SPDIF_STCCA_31_0 0x78 /* SPDIF transmit C channel register, bits 31-0 */
#define REG_SPDIF_STCCA_63_32 0x7C /* SPDIF transmit C channel register, bits 63-32 */
#define REG_SPDIF_STCCA_95_64 0x80 /* SPDIF transmit C channel register, bits 95-64 */
#define REG_SPDIF_STCCA_127_96 0x84 /* SPDIF transmit C channel register, bits 127-96 */
#define REG_SPDIF_STCCA_159_128 0x88 /* SPDIF transmit C channel register, bits 159-128 */
#define REG_SPDIF_STCCA_191_160 0x8C /* SPDIF transmit C channel register, bits 191-160 */

/* SPDIF Configuration register */
#define SCR_RXFIFO_CTL_OFFSET 23
Expand Down

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