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RISC-V: Split out the XIP fixups into their own file
This was broken by the original refactoring (as the XIP definitions depend on <asm/pgtable.h>) and then more broken by the merge (as I accidentally took the old version). This fixes both breakages, while also pulling this out of <asm/asm.h> to avoid polluting most assembly files with the XIP fixups. Fixes: bee7fbc ("RISC-V CPU Idle Support") Fixes: 63b13e6 ("RISC-V: Add arch functions for non-retentive suspend entry/exit") Link: https://lore.kernel.org/r/20220420184056.7886-4-palmer@rivosinc.com Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Palmer Dabbelt
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May 25, 2022
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,31 @@ | ||
/* SPDX-License-Identifier: GPL-2.0-only */ | ||
/* | ||
* XIP fixup macros, only useful in assembly. | ||
*/ | ||
#ifndef _ASM_RISCV_XIP_FIXUP_H | ||
#define _ASM_RISCV_XIP_FIXUP_H | ||
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#include <linux/pgtable.h> | ||
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#ifdef CONFIG_XIP_KERNEL | ||
.macro XIP_FIXUP_OFFSET reg | ||
REG_L t0, _xip_fixup | ||
add \reg, \reg, t0 | ||
.endm | ||
.macro XIP_FIXUP_FLASH_OFFSET reg | ||
la t1, __data_loc | ||
REG_L t1, _xip_phys_offset | ||
sub \reg, \reg, t1 | ||
add \reg, \reg, t0 | ||
.endm | ||
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_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET | ||
_xip_phys_offset: .dword CONFIG_XIP_PHYS_ADDR + XIP_OFFSET | ||
#else | ||
.macro XIP_FIXUP_OFFSET reg | ||
.endm | ||
.macro XIP_FIXUP_FLASH_OFFSET reg | ||
.endm | ||
#endif /* CONFIG_XIP_KERNEL */ | ||
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#endif |
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