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powerpc: Spinlock optimization and cleanup
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This patch optimizes powerpc spinlock implementation by:

* Use the correct EH hint bit on the larx for supported ISA.  For lock
  acquisition, the thread that acquired the lock with a successful stcx
  does not want to give away the write ownership on the cacheline.  The
  idea is to make the load reservation "sticky" about retaining write
  authority to the line.  That way, the store that must inevitably come
  to release the lock can succeed quickly and not contend with other
  threads issuing lwarx.  If another thread does a store to the line
  (false sharing), the winning thread must give up write authority to
  the proper value of EH for the larx for a lock acquisition is 1.

* Increase contented lock performance by up to 40%, and no measurable
  impact on uncontended locks on P8.

Thanks to Adhemerval Zanella who did most of the work.  I've run some
tests, and addressed some minor feedback.

	* sysdeps/powerpc/nptl/pthread_spin_lock.c (pthread_spin_lock):
	Add lwarx hint, and use macro for acquire instruction.
	* sysdeps/powerpc/nptl/pthread_spin_trylock.c (pthread_spin_trylock):
	Likewise.
	* sysdep/unix/sysv/linux/powerpc/pthread_spin_unlock.c: Move to ...
	* sysdeps/powerpc/nptl/pthread_spin_unlock.c: ... here, and
	update to use new atomic macros.
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Paul Murphy authored and Tulio Magno Quites Machado Filho committed Nov 19, 2015
1 parent 86b4939 commit 9695cb3
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Showing 4 changed files with 16 additions and 6 deletions.
11 changes: 11 additions & 0 deletions ChangeLog
Original file line number Diff line number Diff line change
@@ -1,3 +1,14 @@
2015-11-19 Adhemerval Zanella <azanella@linux.vnet.ibm.com>
Paul E. Murphy <murphyp@linux.vnet.ibm.com>

* sysdeps/powerpc/nptl/pthread_spin_lock.c (pthread_spin_lock):
Add lwarx hint, and use macro for acquire instruction.
* sysdeps/powerpc/nptl/pthread_spin_trylock.c (pthread_spin_trylock):
Likewise.
* sysdep/unix/sysv/linux/powerpc/pthread_spin_unlock.c: Move to ...
* sysdeps/powerpc/nptl/pthread_spin_unlock.c: ... here, and
update to use new atomic macros.

2015-11-19 Paul E. Murphy <murphyp@linux.vnet.ibm.com>

* sysdeps/unix/sysv/linux/powerpc/elision-trylock.c
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4 changes: 2 additions & 2 deletions sysdeps/powerpc/nptl/pthread_spin_lock.c
Original file line number Diff line number Diff line change
Expand Up @@ -24,12 +24,12 @@ pthread_spin_lock (pthread_spinlock_t *lock)
unsigned int __tmp;

asm volatile (
"1: lwarx %0,0,%1\n"
"1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n"
" cmpwi 0,%0,0\n"
" bne- 2f\n"
" stwcx. %2,0,%1\n"
" bne- 2f\n"
" isync\n"
__ARCH_ACQ_INSTR "\n"
" .subsection 1\n"
"2: lwzx %0,0,%1\n"
" cmpwi 0,%0,0\n"
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4 changes: 2 additions & 2 deletions sysdeps/powerpc/nptl/pthread_spin_trylock.c
Original file line number Diff line number Diff line change
Expand Up @@ -25,13 +25,13 @@ pthread_spin_trylock (pthread_spinlock_t *lock)
unsigned int old;
int err = EBUSY;

asm ("1: lwarx %0,0,%2\n"
asm ("1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n"
" cmpwi 0,%0,0\n"
" bne 2f\n"
" stwcx. %3,0,%2\n"
" bne- 1b\n"
" li %1,0\n"
" isync\n"
__ARCH_ACQ_INSTR "\n"
"2: "
: "=&r" (old), "=&r" (err)
: "r" (lock), "r" (1), "1" (err)
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Expand Up @@ -22,7 +22,6 @@
int
pthread_spin_unlock (pthread_spinlock_t *lock)
{
__asm __volatile (__ARCH_REL_INSTR ::: "memory");
*lock = 0;
atomic_store_release (lock, 0);
return 0;
}

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